FPGA Journal Update

a techfocus media publication :: January 13, 2004 :: volume II, no. 2

FROM THE EDITOR

Does your design team pay a lot for tools? This week we take a close look at the dynamics of the design tool market for FPGA. Programmable logic designers have come to expect a much lower price tag on design tools than their ASIC counterparts. Is the difference justified? Will the trend continue, or will the newest FPGA architectures require design tools with ASIC-like price tags?

Next week we’ll be looking at the technology that differentiates embedded system design in FPGA from embedded system design in ASIC. Embedding debugging and analysis modules in your design isn’t just a good idea. It’s probably the only way you have a chance of getting your custom hardware and software to work together with all the peripherals, memory, IP, and bus structures you’re planning to put on your device.

Thanks for reading!

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Kevin Morris – Editor
FPGA and Programmable Logic Journal

To Buy or Not to Buy - Will FPGA designers pay ASIC prices for EDA tools?

In the early ASIC market, the silicon suppliers initially developed their own design tools. They had no choice. Commercial software was not yet available to handle the relatively new and complex tasks required to implement ASIC designs successfully. After a few years, entrepreneurs saw opportunity in developing and marketing general-purpose multi-vendor commercial ASIC tools. The silicon architectures were similar enough that a single tool set could easily adapt to several vendors’ technologies.

The vendor-independent ASIC tool market flourished and gave rise to much of today’s EDA industry. EDA vendors took advantage of two key properties of the ASIC market. First, there was considerable leverage available to commercial tool developers because the cost of development could be amortized over a broad range of vendors’ technologies. There were many ASIC vendors, and none had a commanding market share. Any ASIC vendor developing proprietary tools was at an economic disadvantage compared with commercial EDA. Second, the tool vendor could demand a high premium because ASIC tools, particularly those for design verification, solved a very expensive problem: ASIC NRE. Design teams were willing to pay significant sums for a design tool that could help avoid additional design turns costing tens to hundreds of thousands of dollars and weeks of schedule time.

The fledgling FPGA market came out of the chute differently. First, there was a much smaller number of silicon suppliers. Only a handful of FPGA vendors existed, and only a couple maintained dominant market share. In addition, the architectures varied significantly from vendor to vendor, so creating tools to support a particular vendor was a highly customized affair. This eliminated the leverage needed to give commercial EDA an advantage by spreading development across a number of vendors. An FPGA vendor with double-digit market share had enough designer audience to invest as much in tool development as commercial EDA, or more in some cases. [more]

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