Your next design project requires some sort of custom IC. The device will aggregate several functions from your previous-generation product and needs to meet some modest power and performance improvement goals. Your company is going to produce probably a hundred thousand units of this design, maybe more if it is successful. The complexity and speed of the device would require a fairly expensive FPGA, pushing the unit cost to a point that would erode and possibly eliminate your profit margins. On the other hand, the cycle time, NRE, and risk of doing a cell-based ASIC are a stretch for your team and could be a showstopper for the project. You may be a customer for the new breed of semi-custom logic known as structured ASIC.

While FPGA costs have been dropping, the high-end devices have remained expensive, power-hungry, and somewhat performance- and density-limited compared with ASIC devices. New super-low-cost generations of FPGAs, while far more affordable than their high-end cousins, are deliberately limited in their capabilities in order to preserve the margin of the flagship devices. Applications that require the performance of high-end devices with volumes and price structures that demand the prices of the low-cost devices fall into a gap not well served by the current programmable-logic industry. At the same time, cell-based ASIC technology is skyrocketing away from this group as well, with increasing NRE, longer schedules, and higher risk factors.

These factors have combined to create a niche for a new kind of semi-custom mask-programmable device known as structured ASIC. Structured ASIC devices probably most closely resemble gate arrays as they are pre-manufactured and mask-customized by the addition of only a few metal layers. Where they differ from gate arrays is in the pre-fabricated cells. In addition to random logic fabric, structured ASIC devices come with a number of available larger-scale IP blocks pre-designed on the device. For the design team, this means less design, testing, and integration time, and lower NRE and mask costs. If the available IP is a good fit for your application (and here is the current Achilles’ heel), performance and power consumption can be comparable to a full-boat ASIC implementation. Compared with FPGA, a structured ASIC implementation offers potentially lower unit cost, higher performance, lower power consumption, and a smaller footprint. [more]

Domain-Specific Platform FPGAs
by Per Holmberg, Xilinx, Inc.

ASIC NRE costs and design times are skyrocketing. At 130nm, NRE can be $10M or more and the time needed to design an ASIC chip typically ranges from 12-18 months. In addition, application adaptability is often being included in the chip’s specifications. The need for adaptability is driven by several factors, including:
• A shift in the target market, often significant, during the year-plus design cycle for an ASIC
• Rapidly evolving standards, particularly for communications equipment
• Product differentiation, particularly for a range of products derived from a common platform
• Hardware reuse for succeeding product generations

Designers are turning to less costly alternatives than ASICs to reduce the time and financial resources they need to design a complex system-on-a-chip (SoC). Gartner Dataquest projects that ASIC sales will show an 8.4% compound annual growth rate between 2002 and 2007. More importantly, however, Bryan Lewis, Dataquest's chief analyst for ASIC, SoC, and FPGA research, notes that ASIC design starts will continue to decline, from more than 11,000 in 1997 to fewer than 4,000 in 2006. In contrast, a study from iSuppli forecasts much larger double-digit growth in the FPGA market—15.9% in 2003, 25.6% in 2004, and 26.4% in 2005. Further demonstrating the shift to FPGA designs, Hier Design’s Jackson Kreiter, in a September 1, 2003 EEdesign article, Why EDA shouldn't ignore FPGAs, notes, “In 2002, there were 90,000 FPGA design starts, which represents a more than 10-to-1 ratio over ASIC design starts.” [more]

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