a techfocus media publication :: December 16, 2003 :: volume I, no. 12

FROM THE EDITOR

Happy Holidays! This week sees renewed health in the FPGA market as a number of announcements hit the wires from a variety of both new and established providers. At the same time, the structured-ASIC idea is picking up steam, and should continue to do so throughout 2004. Our new feature article this week talks about the lingering stigma surrounding FPGA design in the engineering community.

Next week, we explore the myth and the reality of in-system re-programmability. Do designers make use of this well-hyped feature of programmable logic, or do design realities make re-programmability impractical?

Thanks for reading!

If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal


LATEST NEWS


Tuesday, Dec. 16, 2003

Hier Design's PlanAhead Named to EDN's Top 100 Products of 2003 Listing; Hierarchical Floorplanner Offers FPGA Designers an ASIC-Style Design Methodology

Altera Meets OBSAI RP3 Interface Specification for Cellular Base Station Architecture

MathStar and Summit Design Release Visual Elite SystemC Libraries Targeting The Revolutionary FPOA(TM) Technology


Monday, Dec. 15, 2003

Aptix Introduces Pathfinder IP Validation Station; Low Cost Unit Incorporates Altera Stratix FPGA

Aptix Joins Altera Access Partners Program; Partnership Facilitates Delivery of Leading Edge Design and Verification Solutions

Synplicity Adds Improvements to Industry's Only RTL Debugging Software for FPGAs

QuickLogic and TimeSys Partner to Deliver Embedded Linux RTOS and Development Tools for QuickMIPS Products

Altera MAX CPLDs Power Popular Cellular Phone Cameras

GDA Technologies Selected by QLogic for PCI Express Cores

Xilinx Delivers World's First FPGA-Based DSP Software Tool with JTAG Interface - Expands Customer Access to XtremeDSP Solution


Thursday, Dec. 11, 2003

Programmable Logic Reduces System Costs: Learn How at Altera Net Seminar

Xilinx and Intelliga Announce Low Cost Automotive Lin Bus Solution Using Spartan-3 FPGAS


Wednesday, Dec. 10, 2003

Thales e-Security Introduces 100Mbps High-Speed IP Encryptor

Xilinx Spartan-3 Devices Enable High Performance DSP Functions at Breakthrough Low Cost Price Points

Napatech and Xilinx Announce World's First 10 Gbps Programmable Ethernet Adapter

NEC Electronics and Cadence Announce Encounter Platform to Support NEC Electronics' ISSP Structured ASIC Platform

CURRENT FEATURE ARTICLES

Stigmata
Does your business card still say ASIC Designer?
Databahn

High-speed serial I/O for programmable logic
Going Serial with your Backplane
by Jock Tomlinson, Lattice Semiconductor
Design-in Kits Simplify Serial PCB
by Brad Griffin, Cadence Design Systems
Patently Unobvious

How the patent system works for and against technology
Embedded Dilemma
Platforms, soft-cores, RTOS, oh my!
Bringing the Processor into the FPGA
by Rob Irwin, Altium Limited
Language Barrier
How will the next generation of FPGAs be designed?
What's the Right Language for DSP System-Level Design?
by Tom Feist, VP of Marketing, AccelChip, Inc.
Board with FPGAs
Challenges getting your FPGA to work - on your board

Stigmata - Does your business card still say ASIC Designer?

In even the driest, most highly technical areas, there is culture. The culture of engineering communities is elusive because engineers as a group tend to be highly intelligent, often introverted personalities. Nonetheless, a culture (defined as the predominating attitudes and behavior that characterize the functioning of a group) does exist. In this culture, as in most, human traits such as ego and vanity play major roles.

I was at a technical conference listening to a paper on high-level design methodologies with FPGA. The engineer seated next to me worked for a global systems company. He leaned over and asked me several questions about the paper. The presentation was in English, which was not the native language of either the speaker or my neighbor. We exchanged business cards, and I noticed that his said “ASIC designer”. I had heard more than a year earlier that his company had a “no more ASIC” policy. Because of rising NRE and risks, new design starts were being diverted to FPGA. When I asked about this, the young engineer immediately went on the defensive: “I am still ASIC designer, just this year we are doing FPGAs instead.”

This attitude, it turns out, is pervasive among engineers. ASIC design has long been the prestigious assignment, and any change in that perception is lagging the shift in technology. Creating a system-on-chip design with one of today’s leading-edge FPGA technologies is a challenging and daunting task. Using the technology, tools, and techniques available to FPGA designers, a talented team can have a single-chip solution with an embedded 32-bit processor, software, peripherals, RTOS, and high-speed I/O up and running on a prototype board in matter of a few weeks. Engineering-wise, this same task would take the average ASIC design team months, possibly years, to accomplish. [more]

Visit Techfocus Media


You're receiving this newsletter because you subscribed at our website www.fpgajournal.com.
If at any time, you would like to unsubscribe, send e-mail to unsubscribe@fpgajournal.com. (But we hope you don't.)
If you have any questions or comments, send them to comments@fpgajournal.com.

All material copyright © 2003 techfocus media, inc. All rights reserved.
Privacy Statement