a techfocus media publication :: December 9, 2003 :: volume I, no. 11

FROM THE EDITOR

Welcome! We charge toward the end of the year with three feature articles this week discussing the ins and outs of high-speed serial I/O. First, we survey the standards and protocols available for various data transfer applications. Next, Jock Tomlinson of Lattice Semiconductor gives us a rundown on the technology behind high speed I/O, and Brad Griffin of Cadence explains the value of design-in kits in routing differential signals on your PCB.

Next week we ask whether field re-programmability is a useful feature of programmable logic, or vendor-hype that never really makes it into practice.

As the new year approaches, we’re looking for design teams with stories to tell of complex FPGA and System-on-Programmable-Chip designs. If you’ve tackled and tamed the beast, drop us a line and let us know.

Thanks for reading!

If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Kevin Morris – Editor
FPGA and Programmable Logic Journal

LATEST NEWS

Tuesday, Dec. 9, 2003

Xilinx Appoints Intel Executive to VP of Operations Post


Monday, Dec. 8, 2003

Hier Design Names Craig Robbins Vice President of Sales; Assumes Responsibility for Worldwide Sales Activities

IDT, Xilinx and P-Cube to Present NetSeminar on Data-Flow Management Solutions

EDA Tools Startup Bluespec Inc. to Elevate and Accelerate Chip Design

Large International Presence Highlights Software Defined Radio Conference

Ultimodule Introduces Portfolio of Open Modular Building Blocks for Embedded Systems

Xilinx Unveils Revolutionary FPGA Architecture, Enables Next-Generation Platform FPGAs

Actel Enhances Libero Tool Suite to Boost Performance and Support for Proasic Plus FPGAs

Altera HardCopy Devices Speed Development of New Motorola Horizon II BTS Portfolio

Learn How to Leverage FPGAs for Image Processing at Altera Net Seminar


Friday, Dec. 5, 2003

Seodu Inchip to Provide Ricreations Inc.'s Universal Scan JTAG Tool in Korea


Thursday, Dec. 4, 2003

Actel's Protocol Design Services Group Selects HelloSoft's Wireless LAN IP


Tuesday, Dec. 2, 2003

HARDI Electronics Releases a New Single-FPGA Module in the HAPS Prototyping Family; Demand for New Product Led by Texas Instruments' Desire for Increased Capacity

Legacy Electronics Signs BP Sales Inc. as Texas Rep Firm

Xilinx Business Update for December Quarter Fiscal 2004

Actel's Advanced Packaging Technology Delivers High-Density, Programmable Alternative to Known Good Die

High-Density Packaging Solution Further Extends Actel's Reach Into Space and Military Markets

2004 International CES Attracts Top Leaders in Embedded Technology

 


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CURRENT FEATURE ARTICLES

Databahn
High-speed serial I/O for programmable logic
Going Serial with your Backplane
by Jock Tomlinson, Lattice Semiconductor
Design-in Kits Simplify Serial PCB
by Brad Griffin, Cadence Design Systems
Patently Unobvious

How the patent system works for and against technology
Embedded Dilemma
Platforms, soft-cores, RTOS, oh my!
Bringing the Processor into the FPGA
by Rob Irwin, Altium Limited
Language Barrier
How will the next generation of FPGAs be designed?
What's the Right Language for DSP System-Level Design?
by Tom Feist, VP of Marketing, AccelChip, Inc.
Board with FPGAs
Challenges getting your FPGA to work - on your board

Databahn - High speed serial I/O for Programmable Logic

Suppose you travel by car. In order to get around, you need certain expertise and equipment, such as a license, maps, experience, and a car. Now suppose you want to get places faster. You’ll need more skill, a faster car, better routes, and possibly a way to avoid running afoul of the law. As you push the speed envelope more, the demands and risks increase dramatically.

Moving data around through a parallel bus or backplane is much the same story. The faster you go, the more design skill and attention to detail is required. Creepy problems like clock synchronization and signal integrity start to grow into unmanageable monsters.

At some point you need to make a break. You need to travel by air. If you fly, the demands on your expertise diminish, while your speed increases dramatically. You book the flight and get yourself to the airport at the appointed time, and someone else handles the rest. Sure, enormous complexity is involved in hurling you along ten thousand meters above the earth at near the speed of sound, but you don’t have to worry about that. Someone else handled all that complexity before you entered the picture. Welcome to the world of high-speed serial I/O. If you buy the right ticket, your data can be blasting along between devices, cards, or racks faster than you can say SerDes, and your FPGA vendor will have already worried about all the complexity for you ahead of time. [more]

Legacy Parallel to Serial Backplane Design and Considerations

Parallel digital interconnect and backplanes have existed since the advent of modern electronic systems.

PCI has emerged as the most pervasive interconnect and backplane drive technology, which was first introduced in the early 1990s as a chip-to-chip interconnect standard based on 32 bits of data that operated at 33 MHz on these modern systems. PCI has evolved over the years from 32 bit/33Mhz to 64 bit/66MHz, to most recently, 64bit/133MHz, with plans to migrate up to 266 MHz and beyond in the future.

Many system design engineers viewed PCI, as a vehicle to address not only their chip-to-chip interconnect design requirements, but also to migrate PCI into the backplane for board-to-board interconnect as well. PCI was never designed nor intended to be used in backplane applications or even in mid-plane interconnect applications. Nevertheless, many design engineers successfully deployed systems that utilized PCI as not only the chip-to-chip interconnect, but also as the board-to-board (backplane) interconnect. [more]

Design-in Kits Address Challenges of Multi-Gigabit System Interconnect

After performance requirements for a system have been established, selecting the right devices to integrate into the system is an important and time-consuming part of the high-speed product design cycle. Careful attention to interconnect constructs is required when selecting devices capable of moving data around a system at gigabit data rates. Many IC companies spend significant effort providing written documentation that guides users on how to design interconnects that work with their devices. Systems companies must then spend considerable time reading and interpreting the documentation in order to evaluate performance of various devices before moving on to the board/system design.

For the PCB or systems designer, the size, cost and performance of each device is carefully considered in spite of stringent time-to-market pressure. . The design guidelines from IC companies are typically documented in a combination of terminology—some of the terms may be very familiar to the electrical engineer and some, less familiar to the PCB designer. On the other hand, some of the documentation will be more in line with typical terminology used by the PCB designer and less so by the electrical engineer. [more]


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