| CURRENT
FEATURE ARTICLES
Language
Barrier
How will the next generation of FPGAs be designed?
What's
the Right Language for DSP System-Level Design?
by Tom Feist, VP of Marketing, AccelChip, Inc.
Board
with FPGAs
Challenges getting your FPGA to work - on your board
Getting Physical
New physical design tools target FPGA
Corralling
the Complexity of FPGAs
by Jackson Kreiter, of Hier Design, Inc.
Glue
to Glory
How three innovations are changing the face of FPGA design
Pinching
Pennies
Low-cost FPGAs target consumer applications
Design
Tool Quandary
Which design-tool flow is right for your project?
Beyond
Processors
Implementing high-performance DSP algorithms in FPGA
In
1995, the future was clear. During the prior decade, digital ICs
had grown from thousands of gates to hundreds of thousands, and
thus design had outgrown the schematic diagram. Fortunately, with
the advent of hardware description languages and tools to simulate
and synthesize them, our level of abstraction had been raised. We
could now describe in a few hundred lines of VHDL or Verilog what
had previously taken hundreds of pages of painstaking graphical
schematic entry. Life was good. Leverage was gained. Obviously,
then, by the end of the next decade, we’d all have chased
Mr. Moore to the next level of abstraction with another 10X boost
in productivity.
Well,
there’s still the guy with the sandwich sign on the corner
reading “Behavioral Synthesis is Nigh!” but the rest
of us have grown more skeptical over the past few years. Where is
the promised land of 100K gates per line of code?
Despite
promises that both rival and resemble those of cold-fusion, no company
has yet successfully marketed a production-worthy design tool flow
that can produce and verify high-quality designs from behavioral
descriptions. The design community is a pragmatic one that won’t
leap to a new methodology based on promises alone. There must be
a clearly demonstrated track record of improved productivity to
justify a difficult and expensive methodology switch, and high-level
language design has yet to accomplish that. [more]
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To
survive our current economic climate, companies now, more than ever,
need to do more with less. Recent downsizings, coupled with extreme
time-to-market pressures, are forcing leading commercial, military,
and aerospace companies to investigate all facets of their design
process to gain that first mover advantage. To expedite development,
forward looking companies are seeking solutions to augment current
flows based on general purpose design languages such as C++, SystemC,
VHDL, and Verilog with new flows that enable the algorithm design,
chip design, and subsystem design to be verified early and often
against system-level models. It is no longer sufficient to design
in isolation.
This
demand for greater productivity has given rise to a new set of domain-specific
languages (DSLs) that promise a superior solution for system-level
design. DSLs are programming languages that sacrifice generality
for suitability to a particular problem area. By reducing the conceptual
distance between the problem space and the language used to express
the problem, programming becomes simpler, easier, and more reliable.
The amount of code that must be written is dramatically reduced,
increasing productivity and decreasing maintenance costs. Well architected
DSLs not only provide constructs that allow concise representation
of large design objects, they also come complete with visualization
tools tuned for the specific design domain and provide links to
the hardware and software implementation processes. [more]
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