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FEATURE ARTICLES
Board with FPGAs
Challenges getting your FPGA to work - on your board
Getting Physical
New physical design tools target FPGA
Corralling
the Complexity of FPGAs
by Jackson Kreiter, of Hier Design, Inc.
Glue
to Glory
How three innovations are changing the face of FPGA design
Pinching
Pennies
Low-cost FPGAs target consumer applications
Design
Tool Quandary
Which design-tool flow is right for your project?
Beyond
Processors
Implementing high-performance DSP algorithms in FPGA
Evaluating
Performance
FPGAs vs. DSPs, by Jeff Bier, BDTI
Making
the Transition
FPGA Primer for ASIC designers
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Somewhere,
in another building perhaps, is another engineer just like you.
He spends every day working on the same project as you. He went
to engineering school just like you did. He even hooks up his logic
analyzer one probe at a time just like you. You probably don’t
go to the same cocktail parties, however, and chances are you don’t
sit together at company picnics. In fact, he may be thinking bad
thoughts about you right now. Why? Because while Moore’s law
may work just fine for you, it generally makes his life more difficult,
and your new 1500- pin FPGA may be the scourge of his professional
life these days. He’s the guy designing the board that your
new super-duper Stratix GX or Virtex-II Pro will park on, and you
need to find out what his problem is before it’s too late.
In
the good-old days when “deep-submicron” meant 0.8µ,
and “high pin-count” meant a 256PGA, the board designer
didn’t have to worry too much about FPGAs. Even though almost
every printed circuit board contained at least one programmable
logic device (and still does) the FPGA never caused too much heartburn.
Now that we talk about nanometers instead of microns and we have
pin numbers with four digits, however, the picture has changed.
We need to examine the effects of modern FPGA packaging and performance
on printed circuit board design, and look at ways to mitigate the
problems.
First,
let’s look at the administrative issues. The board schematic
is typically maintained by a different team than the one designing
high-end ASIC and FPGA. In ASIC design, the pin-out is usually nailed
down early in the design process and doesn’t change much as
the project progresses. In the case of FPGA, however, the pin-out
is constantly changing. Moving I/O assignments around on the device
is an easy way to solve many timing problems, and FPGA design teams
regularly take advantage of this flexibility. Down in board-land
this is not well received. [more]
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