| CURRENT
FEATURE ARTICLES
Getting Physical
New physical design tools target FPGA
Corralling
the Complexity of FPGAs
by Jackson Kreiter, of Hier Design, Inc.
Glue
to Glory
How three innovations are changing the face of FPGA design
Pinching
Pennies
Low-cost FPGAs target consumer applications
Design
Tool Quandary
Which design-tool flow is right for your project?
Beyond
Processors
Implementing high-performance DSP algorithms in FPGA
Evaluating
Performance
FPGAs vs. DSPs, by Jeff Bier, BDTI
Making
the Transition
FPGA Primer for ASIC designers
There
comes a point when it’s time to take your relationship with
your FPGA to the next level; a time when you can no longer be separated
from the intimate details of your implementation by the push of
a button; a time when you need to get past the summary report and
understand what that negative slack is really all about. It’s
time to get physical with your FPGA design, and it happens to many
design teams when they cross the one-million gate threshold.
In
the happy, carefree days when programmable logic was simple and
designers barely had time to grab coffee after pressing the “go”
button on their automated tool suite, timing issues were concentrated
in the logic, and no one thought much about the consequences of
parasitic, routing-induced delays. If you needed to change your
design, you held a quick design review with yourself, updated a
few lines of RTL, and tossed the design back at the automated tools
again, confident that your results would be just as good as the
previous run and you’d be home in time for dinner.
Today,
however, the situation has started to deteriorate. Now routing contributes
the lion’s share of the delay, and, as a result, the accurate
timing estimates you enjoyed back in the old days have left town
and been replaced by wild, unpredictable plus-or-minus 30% beasts
that leave you staring at a different harrowing list of critical
paths every time you run your design through your tool suite. Just
when you get close to meeting all your timing specs, you make a
tiny design change that throws everything back up in the air. The
first thing you know, you’re back underwater again with more
timing violations than before. In addition, the piece of IP you
brought over from the ASIC team that needs to run at 66MHz (you
know the one) is now running at 53.125.
[more]
Due
to the ever-increasing costs of semiconductors and time-to-market
considerations, field programmable gate array (FPGA) design starts
have shot past application specific integrated circuits (ASICs)
design starts. ASICs are now out of reach for an ever-growing number
of product applications due to skyrocketing mask costs, prolonged
time-to-manufacturing, risk of re-spins and inventory costs. As
a result, it is becoming increasingly harder for design houses to
justify an ASIC over an FPGA implementation.
The increased use of FPGAs, which have reached multi-million gate
complexity mark, is causing designers to encounter problems once
limited to ASIC design. For example, FPGA designers are still using
electronic design automation (EDA) software created when flattened
designs were easily managed, though it is no longer practical to
design FPGAs flat –– that is, without hierarchy. [more]
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