CURRENT FEATURE ARTICLES
Glue to Glory
How three innovations are changing the face of FPGA design
Pinching Pennies
Low-cost FPGAs target consumer applications
Design Tool Quandary
Which design-tool flow is right for your project?
Beyond Processors
Implementing high-performance DSP algorithms in FPGA
Evaluating Performance
FPGAs vs. DSPs, by Jeff Bier, BDTI
Making the Transition
FPGA Primer for ASIC designers

For years, programmable logic has been the Cinderella of the ASIC family – left to clean up the scraps while the “real” ASICs got the glory and did all the important work. This best-supporting-actor role flowed into many design teams too, where the less experienced engineers were relegated to FPGA duty, while the superstars got to work on the ASIC.

As ASIC costs skyrocketed, however, many companies started to look at the feasibility of using FPGAs for more than just consolidating the leftover logic from the project that couldn’t, for some reason, go on the ASIC. While the FPGA solution would solve many of the most difficult problems with ASICs: frequent revisions, long lead times, huge NRE charges, and moving standards, FPGAs had their own limitations that prevented them from being useful in key roles in many, perhaps most, applications. Aside from the well-known cost, gate-count and operational-frequency limitations, FPGAs were power-hungry, lacked the rich libraries of IP available on ASICs, had little or no memory flexibility, and couldn’t get data on and off the chip at the required speeds.

Today’s high-end FPGAs (and, as we discussed in our “Pinching Pennies” article, even many new very-low-cost ones) have addressed these issues and are finding their way into a central role in more and more systems. FPGA manufacturers have delivered this capability, thanks in part to three quietly revolutionary innovations: high-speed smart I/O, flexible memory architectures, and hard/soft IP libraries.

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