a techfocus media publication :: October 14, 2003 :: volume I, no. 3

Your FPGA vendor gives you a set of design tools free with your subscription. Your company has an ASIC flow that’s maintained by your internal CAD group. Your local EDA representative tells you that you really need vendor-independent tools that cost 5 times the price to get the most out of your design team, but their biggest competitor is offering “special edition” tools for 2 milk-carton tops, a newspaper coupon, and proof of your registration at the Design Automation Conference…

How do you figure out the best design flow for your FPGA design project? How much of the available information is hype, and how much is meaningful? As a project manager, with cost per engineer running about $200K(US) per year, do you care if your design tool costs $1K or $100K? Are more expensive tools any better? Do the vendor’s tools work better on their own technology? Are they just designed to lock you in so you can’t migrate to another vendor’s part? How do you justify your decision?

Let’s look at the options for FPGA design tools. We’ll examine which tools are in the “required” bucket, which are “nice to have,” and how to choose the best of each to fit your needs.

First, it helps to have a top-level view of the FPGA design flow for the type of designs you’re doing. Are you using simple PLDs for glue logic? Are you designing a 10-million-gate system-on-chip FPGA with embedded processors and soft IP? Will you retarget your designs to ASICs or possibly to another vendor’s technology? All of these factors influence the design tool environment you choose and can dramatically affect your cost and, more importantly, your results. In this article, we’ll examine the basic tools you’ll use for most medium-to-large complexity designs. Future articles will focus in more detail on specialized tools you’ll need as you move farther toward the leading edge of FPGA design.

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Welcome to week three of FPGA Journal Update. This week, our focus is on choosing the best design tool flow for your FPGA team. With the wide variety of design tools available for programmable logic designers, it's difficult to select a set of tools that will maximize your team's productivity and help you deliver the best possible design on time. Our article should unravel some of the mystery and get you on your way to design environment nirvana.

Since last week, we’ve received a great deal of feedback from readers on both sides of the FPGA vs. DSP processor front. On one hand, readers commented that we could have pointed out more clearly that the benefits of FPGA for DSP primarily kick-in on high-bandwidth, parallelizable applications, and that FPGAs may in fact give worse power and cost performance if used where a single-chip DSP solution will suffice. From the FPGA side, we hear that our article didn’t give enough attention to the new super-low-cost FPGAs now available, and how those change the price/performance calculation. We hope next week’s article on low-cost FPGAs for high-volume applications will give people even more to think about on the topic.

We welcome your feedback. If there's anything we can do to make our publications more useful to you, please let us know at: comments@fpgajournal.com

Thanks for subscribing!

Kevin Morris
Editor - FPGA and Programmable Logic Journal

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