HOME :: JOB
LISTINGS :: WEBCASTS :: ARCHIVES :: MEDIA
KIT :: SUBSCRIBE :: FORUMS
EMBEDDED TECHNOLOGY JOURNAL :: IC JOURNAL |
|
|
|
Synfora Presents Seminar to Aid SoC and FPGA Developers Design High-Performance Video EnginesMOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Synfora Inc., the premier provider of algorithmic synthesis tools used to design SoCs and FPGAs, will conduct a seminar on the morning of Tuesday, December 9, 2008, to show SoC and FPGA developers of video IP how to reduce design and verification time while being able to explore alternative implementations that will let them decrease silicon area and power consumption. The seminar will be conducted by a video expert who has assisted in the architecting and implementing of several leading-edge multi-standard video engines. The seminar will be held at the Santa Clara Techmart Meeting Center from 10:00 AM to 12:00 PM, with lunch being provided from 12:00 to 1:00. Who: Registration for the seminar is now open at http://www.synfora.com/seminar/index.html. About Synfora Inc. Synfora, Inc. is the premier provider of algorithmic synthesis tools used to design complex systems-on-chips (SoCs) and FPGAs. Synfora's technology helps to reduce design costs, dramatically speed chip development, and reduce time-to-market. Synfora serves customers worldwide in the audio, video, imaging, wireless, and security segments of the integrated circuit (IC) design market. The company's investors are ATA Ventures, Foundation Capital, U.S. Venture Partners, Wafra, and Xilinx. For the latest information on Synfora, please visit http://www.synfora.com.
|
|
|
| ©2008 Business Wire. All of the news releases contained herein are protected by copyright and other applicable laws, treaties and conventions. Information contained in the releases is furnished by Business Wire's members, who warrant that they are solely responsible for the content, accuracy and originality of the information contained therein. All reproduction, other than for an individual user's personal reference, is prohibited without prior written permission. |
|
|
All
material on this site copyright © 2003-2008 techfocus media, inc.
All rights reserved. FPGA and Structured ASIC Journal Privacy Statement |