Source: Renesas Technology Corp.
December 4, 2008

Renesas Technology Develops IP Supporting PCI Express® 2.0 High-Speed Serial Interface Standard

One of first in industry to obtain Rev. 2.0 certification

Tokyo, December 4, 2008 — Renesas Technology Corp. today announced the development of logical and physical layer intellectual property (IP) conforming to PCI Express®*1 Base Specification Revision 2.0 (PCI Express 2.0), a high-speed serial interface standard.
PCI Express 2.0, the newest version (Rev. 2.0) of the PCI Express standard, supports high-speed data transfer at up to 5.0 gigabits per second (Gbps).

The new IP was one of the first for the logical and physical layer to be received Rev. 2.0 certification at Compliance Workshop #62 (September 8 through 12, 2008), sponsored by the standards body PCI-SIG®,*2 and supports the 65 nm process node. LSIs incorporating this IP will enable easy connection to other devices supporting the PCI Express 2.0 standard, enabling developers to create systems with high-end graphics processing capabilities.

< Product Background >

Peripheral Component Interconnect (PCI) is an interface for connecting the microprocessor of a personal computer (PC) with peripheral devices and peripheral equipment. A parallel transfer interface standard specified by PCI-SIG, PCI is in widespread use as a standard PC interface. A large number of peripheral device products support the PCI standard.

However, as PC performance was improved year by year, graphics and other applications that handle large volumes of data are becoming more numerous. Data volumes were expected to continue to increase, rendering the transfer performance of PCI insufficient. This led PCI-SIG to develop a next-generated interface standard called PCI Express to support high-speed serial data transfer. Currently a large number of products are compatible with Rev. 1.1, which supports a maximum data transfer speed of 2.5 Gbps. Nevertheless, applications in fields such as graphics and storage demand large-volume data transfers at even wider bandwidths. The newly established Rev. 2.0 provides high-speed data transfer up to twice as fast as Rev. 1.1, and the number of products supporting Rev. 2.0 is anticipated to increase rapidly.

At the same time, there is demand in the embedded field for a standard interface for connecting peripheral devices, LSIs, etc., from the viewpoint of larger-scale systems and increased development efficiency. For this reason, LSIs for embedded applications have started to offer PCI interface functions, enabling use of the many PCI-compliant peripheral devices developed for PCs. In addition, embedded devices for fields such as multimedia now require the ability to transfer large data volumes at speeds on a par with PCs. This has resulted in expanded demand for PCI Express support.

Renesas Technology has developed IP supporting a variety of interfaces, including PCI, and has steadily expanded its product lineup, increasing its market share and accumulating valuable expertise in the process.

Renesas Technology developed and obtained certification of IP supporting Rev. 1.1 of PCI Express, and has released microprocessor and SoC (System on Chip) products incorporating it. Now the company has developed IP supporting the new PCI Express 2.0 standard, which delivers high-speed data transfer at twice the rate of PCI Express 1.1.

< Features >

The features of the IP are summarized below.

(1) Officially certified as supporting the latest PCI Express standard, Rev. 2.0
PCI Express is a high-speed serial interface employing differential signaling. The maximum transfer speed of the latest Rev. 2.0 standard is 5.0 Gbps, double that of the earlier Rev. 1.1 (2.5 Gbps). This translates into high-speed data transfer at an effective rate of 500 megabytes per second per lane.*3 For this reason, more sophisticated and difficult design technology is required to realize circuits that can handle Rev. 2.0.

Renesas Technology previously developed and employed in products IP supporting Rev. 1.1. The expertise and high-level technical ability built up though past development work was applied in the realization of the new IP supporting Rev. 2.0 and the 65 nm process node. This IP is among the first in the industry to receive Rev. 2.0 certification.

By using microprocessor or SoC products incorporating this certified IP, developers can create high-speed systems capable of transferring large volumes of data very rapidly.

(2) Reduced power consumption

The new IP implements an upconfiguration*4 function that dynamically switches the transfer rate during operation. As specified in the PCI Express 2.0 standard, this function enables dynamic switching as follows:

1. When high-speed data transfer is required, multiple lanes each operate at the maximum transfer speed of 5.0 Gbps.

2. When the transfer volume is lower, priority is given to reduced power consumption. Only one lane operates at a transfer speed of 2.5 Gbps, which is half the maximum rate.
The new IP achieves power consumption up to 50% less than Renesas Technology’s earlier IP supporting Rev. 1.1. The combination of the existing power management function and the new upconfiguration function contribute substantially to reduced power consumption for the system overall.

(3) Ability to select function options to suit specific applications
When the new IP is incorporated into products such as MCUs or SoCs, customers will be able to select function options suitable for their target systems.

The main function options will include device attributes (root port/endpoint*5 selection), maximum payload size,*6 number of virtual channels,*7 number of functions,*8 on-chip buffer size, and number of lanes. By combining these options appropriately, customers will be able to realize an LSI that is ideal for the system they are developing.

Renesas Technology plans to release the first products incorporating the new IP in 2009, for systems in fields such as graphics and storage demanding the capability to transfer larger volumes of data. The company plans to eventually extend the IP to process nodes even finer than 65 nm, and to provide enhanced functionality targeted toward key applications, such as an increased number of lanes.

Renesas Technology will promote a system environment evaluation, including the PCI-SIG Compliance Program, to facilitate development work by customers.

< Notes >
Notes: 1. PCI Express is a high-speed serial data transfer standard established by the standards body PCI-SIG. The latest official version is Rev. 2.0, which was preceded by Rev. 1.0, Rev. 1.0a, and Rev. 1.1. Rev. 1.1. was a data transfer standard with a maximum speed of 2.5 Gbps, and Rev. 2.0 boosts the maximum speed to 5.0 Gbps.
2. PCI-SIG (Peripheral Component Interconnect - Special Interest Group): The standards body that specifies standards related to the Peripheral Component Interconnect (PCI) computer bus.
PCI-SIG® and PCI Express® are registered trademarks or service marks of PCI-SIG.
PCI-SIG Web site URL: http://www.pcisig.com/
3. Lane: PCI Express implements serial transfer using point-to-point differential signaling. Differential transfer involves communication over two signal lines in each direction and uses independent signal lines for transmission and reception. Thus, a minimum of four signal lines are required for transmission and reception. This minimum configuration is referred to as a lane.
4. The upconfiguration function is newly defined in Rev. 2.0. It enables the number of lanes and the transfer speed to be changed freely.
5. Root port/endpoint: The Root port is the device that controls the PCI Express system overall. It is usually incorporated into a PC. The Endpoint is one of the elements composing the system. Endpoints are usually incorporated into peripheral devices with PCI Express support.
6. Payload size: The amount of data that is moved in a single transfer operation. The maximum payload size is 4 kilobytes.
7. Virtual channels: Each PCI Express device is divided into multiple virtual channels, and each of these channels is assigned a priority. This arrangement makes it a simple matter to assign higher priority to the transfer of data requiring real-time performance, such as video and audio, and to assign lower priority to other data.
8. Functions: Virtual multiple functions can be assigned within each PCI Express device. This makes it easy to implement multiple applications in a single device.