Source: Aion Systems
November 13, 2006

ESL Startup, Aion Systems, Speeds up FPGA design

FPGA design teams can now build high-speed, optimised DSP solutions
directly from Simulink Models using Aion Systems’ Blocksets.
For the first time designers can go directly from a fixed point Simulink model to a
timing-closed, high-speed, low resource count FPGA implementation without
compromise.

The ModelIP Blockset consists of a collection of multi-channel, multi-rate FIR and
CIC filters, and Waveform Synthesis blocks. Collectively they provide solutions for
Digital Front Ends as found in today’s wireless radio systems. The tools have
advanced features such as timing driven high level synthesis to yield up to 500MHz
operation, automatic RTL testbench creation, automated processor interface
synthesis and documentation generation, and scripts for 3rd party tool integration.
Uniquely, the design entry is portable between FPGA families without sacrificing
performance and size. Since the IP blocks use family specific architectures
internally, you get the best performance on both Altera and Xilinx FPGAs.
Engineers can create custom DSP blocks using the ModelPrim Primary Blockset
consisting of basic operators such as multipliers and adders. Users can concentrate
on their algorithmic design, and let automation combine and pipeline the blocks
for optimal performance.

The tools are available for trial and purchase for Matlab R14 and R2006 on Windows
platforms from www.aionsystems.com.

Aion Systems is a startup company based in High Wycombe, UK, founded in 2005.
The company goal is to let designers get the most from FPGAs. “We believe that
many designers do not have the time nor resources to use FPGAs to their full
potential, and yet at the same time are under constant pressure to reduce the
cost of their products. By unifying the design process within the industry standard
Simulink and Matlab tools we can provide real value to large and small customers
alike.”