Source: Aldec, Inc.
February 6, 2006

Aldec Releases Integrated Support for SystemC™ 2.1

HENDERSON, Nevada – February 1, 2006 -- Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, today announced the release of Riviera™ 2006.02. Riviera 2006.02 offers integrated support of SystemC 2.1, incremental compilation for VHDL and Verilog® design modules decreasing compile run times and improved Verilog RTL, Gate and Timing simulation run times. Riviera’s industry-proven VHDL, Verilog, SystemC and SystemVerilog™ mixed-language simulation technology is providing ASIC and high-density FPGA designers a performance-driven solution for the new generation of system-on-chip designs.

SystemC Compilation and Simulation

Riviera adds support of the new SystemC 2.1 version, which is the base of the first official IEEE SystemC standard – IEEE Std 1666-2005. Constantly growing support for SystemC in other tools, such as synthesizers, will be based on version 2.1, Riviera users will have an easier task of interfacing to those tools. The additional benefit for Riviera users is that SystemC and SystemC Verification (SCV) libraries are precompiled, and ready to use with newer, faster versions of GCC compilers, ensuring significantly faster compilations. Compilation time of SystemC designs primarily on Windows platform was decreased on average by 3.3x. The ability to cross-instantiate SystemC, Verilog and VHDL in any combination will allow gradual introduction of SystemC into existing HDL designs, no matter if the user wants to start by adding SystemC design blocks or testbenches.

VHDL Incremental Compilation

Enabling incremental compilation in both VHDL and Verilog allows you to reduce re-compilation times on an average of 60%. The complier decides whether a design unit needs to be recompiled based on source file contents rather than on file modification dates.

Additional Improvements

Additional improvements in Riviera 2006.02 also include improved SystemVerilog Assertions, Code Coverage, and improved Waveform Viewer.

Pricing and Availability

Riviera 2006.02 is available today based on a floating OS-independent license that supports UNIX, Windows® and Linux. Pricing for Riviera 2006.02 begins at U.S. $12,450.00 and is sold directly by Aldec in the U.S. as well as by authorized international distributors. For a FREE evaluation copy of Riviera, go to www.aldec.com/riviera.

About Riviera

Riviera, a high-performance verification tool, is based on Aldec’s industry-proven VHDL and Verilog mixed-language simulation technology and is used by ASIC and high-density FPGA designers for new generation system-on-chip designs. It supports IEEE VHDL 1076-87/93 and VITAL 2000 in addition to Verilog 1364-2001 and SystemVerilog. Code coverage, Waveform Viewer, advanced dataflow, Design Profiler and interfaces to other EDA tools are provided via PLI and VHPI function calls as part of Riviera’s product configuration.

About Aldec

Aldec, Inc., a 21-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX®, Linux® and Windows® platforms. Aldec is dedicated and responsive to serving its customers’ needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec’s strategic objectives. Additional information about Aldec is available at http://www.aldec.com.

Riviera is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.