HOME :: JOB LISTINGS :: WEBCASTS :: ARCHIVES :: MEDIA KIT :: SUBSCRIBE :: FORUMS


BusinessWire
January 03, 2006 04:00 AM US Pacific Timezone

Bluespec Kicks Off 2006 with VLSI 2006 Tutorial, Banquet Keynote; Will Demonstrate ESL Synthesis Solution for Control Logic, Complex Datapaths

VLSI 2006

WALTHAM, Mass.--(BUSINESS WIRE)--Jan. 3, 2006--Bluespec's Shiv Tasker, chief executive officer, and Rishiyur Nikhil, chief technology officer, will present a tutorial titled, "Beyond RTL: Advanced Digital System Design" during the 19th International Conference on VLSI Design (VLSI 2006) today in Hyderabad, India. Bluespec also will exhibit its ESL synthesis toolset for control logic and complex datapaths in chip design during the conference January 5-7.

Additionally, Bluespec Founder Arvind, professor of the Massachusetts Institute of Technology, will discuss "Is Hardware Innovation Over?" as the January 6 banquet speaker.

More information on VLSI 2006 can be found at: http://www.vlsiconference.com/

For more details on Bluespec's participation at VLSI 2006, contact George Harper, vice president of marketing, who can be reached at (781) 250-2200 or via email at george.harper@bluespec.com. Or, visit the Bluespec website located at: http://www.bluespec.com.

About Bluespec

Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolset, the only one focused on control and complex datapaths, allows ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling (781) 250-2200.

Copyright 2006 Bluespec, Inc. Bluespec is a trademark of Bluespec, Inc. All other brands, products, or service names may be trademarks or service marks of the companies with which they are associated.


 

All material on this site copyright © 2006 techfocus media, inc. All rights reserved.
FPGA and Structured ASIC Journal
Privacy Statement