PR Newswire
Sep 6, 2005 07:30 ET

Xilinx Demonstrates Enhanced Triple Module Redundancy Software Tool at MAPLD 2005

WASHINGTON, Sept. 6 /PRNewswire/ -- What: Xilinx Aerospace and Defense Solutions at MAPLD 2005

Where: Reagan Building and International Trade Center Washington D.C.,
Booth #10

When: September 7 - September 9, 2005

Xilinx Booth Demonstrations:

-- TMR Tool: Demonstration of Xilinx TMRTool support for mitigating
single event upsets in designs using FPGAs with embedded processors.
More information on the Xilinx TMR Tool can be found at
www.xilinx.com/products/milaero/tmr/.
-- Partial Reconfiguration: Demonstration of partial reconfiguration
using Xilinx Virtex devices to show the reconfiguration of a portion of
the FPGA device while the rest of the device is still in operation.
(Logo: http://www.newscom.com/cgi-bin/prnh/20020822/XLNXLOGO )

Xilinx Technical Papers:

-- "The Continued Evolution of Re-Configurable FPGAs for Military and
Space Strategic Applications" Presenter: Howard Bogrow of Xilinx
-- "SEU Mitigation in Re-Configurable FPGAs: Picking the Right Tool for
the Job" Presenters: Brendan Bridgford and Carl Carmichael of Xilinx
-- "Using Active Module Reconfiguration to Time-Multiplex Embedded
Processor Peripherals in Virtex-II and Virtex-II Pro Devices"
Presenters: Brendan Bridgford and Brandon Blodget of Xilinx
-- "Single Event Effects Experimentation and Validation Techniques for SEU
Mitigation Methods for Static Latch Based FPGAs" Presenters: Carl
Carmichael and Sana Rezgui of Xilinx, Gary Swift of JPL/Caltech and
Jeffrey George of Aerospace Corp.
-- "The Continuing Impact of Design and Process Hardening on the NSEU
Sensitivity of Advanced CMOS PLD Technologies" Presenters: Joe Fabula,
Austin Lesea, and Ray Matteis of Xilinx
-- "Initial Single-Event Effects Testing and Mitigation in the Xilinx
Virtex II-Pro FPGA" Presenters: J. George of Aerospace Corp, Sana
Rezgui and Carl Carmichael of Xilinx, Gary Swift of JPL/Caltech, G.
Allen of JPL/Caltech, and Carl Carmichael of Xilinx
-- "Radiation-Induced Multi-bit Upsets in Xilinx SRAM-Based FPGAs"
Presenters: Paul Graham Heather Quinn, Jim Krone and Michael Caffrey
of Los Alamos National Laboratory, Sana Rezgui and Carl Carmichael of
Xilinx
-- "Reconfigurable Field Programmable Gate Arrays (FPGAs) for Space --
Present and Future" Presenter: Richard Padovani of Xilinx
-- "Single Event Effects Mitigation of a Soft Embedded Processor in the
Virtex-II FPGAs" Presenters: Sana Rezgui and Carl Carmichael of
Xilinx, Jeffrey George of Aerospace Corp, Gary Swift of JPL/Caltech),
and Kevin Somervill of NASA
-- "Upset Susceptibility and Design Mitigation of PowerPC405 Processors
Embedded in Virtex II-Pro FPGAs" Presenters: Gary Swift and Gregory
Allen of JPL/Caltech, Jeffrey George of Aerospace Corp, Fayez Chayab of
MDRobotics, Sana Rezgui and Carl Carmichael of Xilinx

About Xilinx

Xilinx, Inc. (NASDAQ:XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at www.xilinx.com.

Web site: http://www.xilinx.com/