Source: Impulse Accelerated Technologies
July 25, 2005

Impulse C-to-FPGA Optimizing Compiler Doubles Quality-of-Results and adds Support for Verilog

CoDeveloper™ Version 2.0 improves code optimization and adds Verilog output

Kirkland, WA – July 25, 2005 – Impulse Accelerated Technologies™ today announced release of Version 2.0 of its CoDeveloper™ C-to-FPGA design tool, with new compiler features and improved quality-of-results. Impulse users report optimization improvements of 2X or better with this new version, resulting in generated hardware that rivals hand-optimized designs.

Impulse CoDeveloper allows FPGA algorithms to be developed and debugged with existing C/C++ tools. The software-to-hardware compiler translates C-language processes to low-level FPGA-hardware, while optimizing the generated logic for increased parallelism. The tool unrolls loops and generates loop pipelines to exploit the extreme levels of parallelism possible in an FPGA. CoDeveloper’s Application Monitor™ generates debugging visualizations for highly-parallel, multi-process applications, helping system designers identify dataflow bottlenecks and other areas for acceleration.

Version 2.0 adds support for module generation, allowing hardware IP blocks to be generated from C-language, using named ports to integrate these blocks with their overall design. Version 2.0 also adds Verilog compiler output, while improving the existing support for VHDL. Quality-of-results has been increased by as much as 2X through enhanced instruction scheduling and loop pipelining. Improvements have been made for fixed-width integer support, fixed-point math operations, optimizer reports (including pipeline effective rate estimates), and desktop simulation through updated Application Manager™ and Application Monitor™ interfaces.  New examples and tutorials have also been added.

Support for embedded processors has also improved in Version 2.0, including support for the latest Altera™ and Xilinx™ processors and related software design environments. The included Impulse C™ libraries support abstract software/hardware communication methods including streams, signals and shared memories, allowing software programmers to make use of available FPGA resources for hardware coprocessing without writing low-level hardware descriptions.

About Impulse - Impulse enables true hardware/software programming of FPGAs.  Impulse tools are compatible with Microsoft Visual Studio™; GCC; Synplicity™ Synplify;  Xilinx ISE™ and Platform Studio™; Altera Quartus™ and SOPC Builder™; and IEEE compatible VHDL and Verilog simulators.

Impulse CoDeveloper 2.0 is priced at $2,695 (annual) or $4,995 (perpetual). 30-day evaluations are free to qualified engineers. Visit or contact info@ImpulseC.com.