From the Editor

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FPGAs are increasingly finding places in safety-critical applications. Yet such flexible devices present problems in the certification process. Europe editor Dick Selwood hears how Altera has teamed up with a German certification organisation to simplify things for the user.

You may have noticed a reward for the best, most insightful forum posts. We're giving another away for the best posts in March, so get started posting.

Kevin Morris - Editor, FPGA Journal


Industry News

March 16, 2010

Mentor Graphics to Extend Cooperation with STMicroelectronics for Advanced Chip-Development Design Solutions

March 15, 2010

6A, 4MHz, Synchronous Step-Down Regulator in a 3mm x 5mm QFN

March 12, 2010

Floating Point Math.h Functions Accelerated 2 – 10X on FPGA Hardware, with Impulse C High Level Synthesis Tools

Upcoming DSP for FPGAs Technical Course in May in Munich

March 11, 2010

New UK Distributor for Impulse C to FPGA Compiler

March 10, 2010

Evatronix invites SoC developers to its free technical 8051 and USB seminars in Beijing,China and Hsinchu, Taiwan

16-Bit Quad, SPI DAC with Internal Reference Achieves ±4LSB INL (Max)

March 09, 2010

Synopsys Galaxy Custom Designer Accelerates Analog/Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction

Imec and Synopsys collaborate on 3D stacked IC development

March 08, 2010

Ericsson adds Full PMBus Read And Write Capability to Voltage Regulators

Lattice Ships Over 200 Million ispMACH 4000 CPLD Devices

60V Input Dual Output Synchronous Step-Down DC/DC Controller Draws Only 50µA in Battery-Powered Systems

March 04, 2010

Programmable 2A 2-Cell Supercap Charger with Automatic Cell Balancing in a Compact 9mm2 Package

March 03, 2010

Real Intent Releases Meridian CDC Version 3.0, Strengthens Technology Leadership in Precise and Comprehensive CDC Verification

Xilinx Lowers Cost and Power of High-Performance Video Processing for Industrial Imaging Applications

Synopsys System Studio Speeds DSP Algorithm Development With New Matrix Data-Type Support

Xilinx Simplifies Development of Real-time Ethernet Networks for Industrial Automation Applications

Feature Articles

Measuring Safety, an FPGA at a Time

by Dick Selwood

One of the problems of being an engineer is the compulsion to classify, count and measure things. Not just for professional purposes, but the sort of person who becomes an engineer seems also to be the sort of person who automatically counts, classifies and lists the things they encounter in everyday life. But some things are difficult to measure. Take love – Shakespeare's Mark Anthony proclaims that, “There's beggary in love that can be reckoned.” (Although, perhaps, Elizabeth Barrett Browning displays an engineering streak when she asks, “How do I love thee? Let me count the ways.”)

Safety is another quality that does not lend itself to easy metrics, but it is something that has to be calibrated. We want our cars, our aeroplanes, our homes to be somehow “safe”, and the outcry after we feel we have been let down, as we can see today with the Toyota affair, is ample evidence that this is a general feeling. But the engineers who have to achieve that safety are faced with a vast range of conflicting pressures. If you were building a brand new transportation system, starting from a totally clean sheet of paper, is it socially acceptable to recognise that there is no such thing as absolute safety? At what point do you say, “It will cost $X million to make this safer and it will save one life a year”?  Read More

It's Just Cool

Is Smart Fusion an FPGA? Who Cares?

by Kevin Morris

The Spacetime Continuum

Tabula Explains 3D FPGAs

by Kevin Morris

Cards on the Table

Xilinx Announces 28nm Plans

by Kevin Morris

Paved with Good Intentions

Replacing Judgement with Process

by Kevin Morris

Graphic Composition

by Dick Selwood


Changes in the Wind

Altera Shows 28nm Plans

by Kevin Morris

Fending Off Evil

Protecting Your FPGA Against DPA

by Kevin Morris

A Perfect DSP Storm

BDTi + High Level Synthesis + FPGA

by Kevin Morris

From Pinout to Layout:

The FPGA/PCB Balancing Act

by Daniel Platzker and Paolo Spazzini, Mentor Graphics Corporation


Any reason not to create a test bench

When I hear an engineer tell me that it's unnecessary to create a test bench or simulate a design because it's so small, I inwardly roll my eyes and think "Here we go again."

I figure if it's a really small design, then it's easy to create a really sma...
Posted on 03/10/10 at 12:02 PM
by: raysalemi

Since you opened the door to pri

Since you opened the door to pricing by comparing with a $5 microcontroller, what's the price of a typical SmartFusion device? I'm assuming the $99 dev kit is heavily subsidized to buy new design-ins.
Posted on 03/10/10 at 8:40 AM
by: gabor@alacron.com

Actel SmartFusion

Actel just rolled out SmartFusion - a device that combines an ARM Cortex M3, FPGA fabric, and programmable analog. We wrote about it in a feature article (click here). ...
Posted on 03/09/10 at 7:18 PM
by: kevin

Synthesis?

I'm curious to see what time-multiplexed synthesis will look like.
Posted on 03/09/10 at 6:08 AM
by: raysalemi

Eagerly waiting ...will love to

Eagerly waiting ...will love to test this product..
Posted on 03/06/10 at 4:44 AM
by: Manish Singh

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On Demand

Developing Functional Safety Systems with TÜV-Qualified FPGAs (WHITE PAPER)

Market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs.

Targeting and Retargeting Guide for Spartan-6 FPGAs (WHITE PAPER)

When targeting or retargeting code from a prior design, some considerations should be made to achieve a quicker and more optimal design when selecting a Spartan®-6 FPGA. This white paper identifies and details the appropriate targeting guidelines and other considerations needed to achieve an improved result for these devices.

Xilinx FPGA Embedded Memory Advantages (WHITE PAPER)

The Virtex®-6 and Spartan®-6 architectures feature flexible internal memory resources that can be configured in a variety of different sizes. This white paper details the available features, illustrating the wide array of memory sizes available and shows the trade-off of using different resources to perform memory functions of different sizes.

Simplify Video Processing with IP Cores and Low-Power FPGAs (VIDEO)

Need to get your video processing systems up and running faster? Developing these applications typically requires implementing and connecting several complex functions. Watch this 5-minute video to learn about pre-verified, configurable building blocks that simplify and accelerate the process for building a complex video chain.

Actel SmartFusion: Intelligent, Innovative Integration (WHITE PAPER)

Actel SmartFusion™ Intelligent Mixed Signal FPGAs – Innovative, Intelligent, Integration. Introducing the only device that integrates a flash FPGA, hard ARM® Cortex™-M3-based microcontroller subsystem (MSS) and programmable analog into a complete, integrated solution. Don’t compromise your embedded design. Build the system you want, with all the features you need, on a single-chip solution. Read the White Paper to learn more.

Design Made Easy With Mixed-Signal FPGAs and State of the Art Software Tools (WHITE PAPER)

This paper examines the evolution path for FPGAs with embedded processors, and the design tools that support them, and considers whether engineers need to evolve their techniques to accommodate the integrated silicon or whether they can continue to manage their boundaries at the silicon level instead of the board level. New techniques are available in the embedded mixed‐signal FPGA design flow, but do they smooth the adoption of a fully integrated device? Find out by reading the White Paper.

Simplifying Multi-Rail Power Management for FPGA designers (CHALK TALK)

Designing a multi-rail power subsystem? Make it easy, and protect expensive ICs, such as FPGAs. Complex designs call for powerful and sophisticated solutions without compromising ease and speed of design. Join Amelia Dalton as she talks with Dave Clemens of Linear Technology about how you can easily set up all-in-one supervising, sequencing, controlling and monitoring of multiple power supplies.

Platform Management Using MachXO & ProcessorPM PLDs (Webcast)

PLDs are commonly used in platform management applications for housekeeping and power-up management. In this webcast, we discuss the requirements of PLDs in this scenario and look at some of the advantages of the MachXO and ProcessorPM devices from Lattice. We will also examine some of the convenient tools that Lattice provides for quick evaluation and experimentation of the MachXO and ProcessorPM PLDs.