Lowering The Total Cost of Ownership for Industrial Applications (WHITE PAPER)

Introduction

Facing neverending global competitive and economic pressures that continue to threaten their business models and bottom line profitability, industrial automation and process-control manufacturers are constantly grappling with cost challenges, including:

• Profitability versus R&D investments
• Time-to-market pressures to adapt to changing economic conditions
• Effective use of limited resources to update existing products, replace existing products, or launch new products
• Managing the product life cycle

This white paper uses a design example to help designers-system, hardware and software engineers-understand how they can take advantage of Altera® Cyclone® series FPGAs to realize a lower total cost of ownership (TCO) as measured by development, enhancement, replacement, and maintenance costs over the lifetime of the system. As shown in Figure 1, a lower TCO over time directly contributes to increasing the gross profit, thereby relieving a pressure faced by most of today's design teams.

Figure 1:  Building Blocks that Contribute to Lowering the TCO

FPGAs Lower the TCO

To illustrate how Altera Cyclone series FPGAs contribute to a lower TCO, this white paper uses a drive control application (Figure 2) as an example that can apply to any industrial design challenge a customer may encounter. A typical drive architecture consists of a control module to run the algorithms to generate position and/or velocity set points and to close a control feedback loop. The control module sends these set points to a drive controller that converts them into electrical signals (current or voltage) to drive one or more motors and/or actuators, which generate the torque to move the load or mechanical components in an inverter or servo drive system. Feedback sensors such as encoders and Hall-effect devices (for servo drives) provide the position or velocity of the motor/actuator to the motion controller to close the signal loop.
 

figure 2: A Typical Drive System

Microcontroller unit (MCU) and digital signal processor (DSP) devices are the mainstay of motion-/drive-control architectures today, with FPGA architectures gaining momentum. MCU/DSP architectures enjoy an established user base and established architectures, development tools, and motion-control algorithms used primarily in single-axis drive applications. As the complexity of drive systems and the number of drive control axes and product features increase, MCU/DSP architectures quickly run out of the performance overhead and flexibility needed to keep pace with changing market requirements. As system performance increases, designers can only increase MCU/DSP frequency and optimize the software algorithms to a certain point.

To address this problem, designers use multiple DSP devices, a combination of DSP and MCU devices, or a combination of MCU/DSP devices and/or FPGAs to partition the performance and functions in their design. While MCU/DSP architectures do enable some degree of code reuse, reuse of highly optimized code is a labor-intensive process and is difficult to partition and move to new devices. Therefore, design methodologies based on MCU and DSP devices require heavy hardware and software resources to partition the application function and performance across x number of devices. Depending on the complexity of the software, this approach results in several months to over a year (development time, t) to port the application to the distributed architecture.

Author:  Jason Chiang, Sr. Technical Product Marketing Manager, Industrial and Automotive Business Unit, Altera Corporation

Jason Chiang is a senior technical marketing manager for Altera’s Industrial and Automotive Business Unit, based in San Jose, California. In this role, Jason is responsible for developing marketing strategies and solutions that facilitate the use of FPGAs in industrial applications. Prior to rejoining Altera in 2008, Jason held various product marketing management roles at P.A. Semi and PMC-Sierra. He holds a BSEE from Cal Poly, San Luis Obispo.