Supporting Digital Television Trends with Next-Generation FPGAs (WHITE PAPER)

Question: What do the following items have in common?

• iPhones
• Avatar 3D (James Cameron's new movie)
• Digital SLR cameras
• LCD digital televisions

Answer: They are all evidence that consumers strongly prefer products with "stunning" visuals.

This white paper shows how these trends towards new features and faster introduction rates of new models are fueling increased FPGA use within high-definition television electronics.

Introduction

The digital television market is growing, with the number of liquid crystal display (LCD)-based digital televisions growing at 22% CAGR (Figure 1). More recent forecasts show growth in 2010 of 6% over 2009's 1% decline(1).
 

Figure 1 - LCD Digital Television Growth Rate

Source: iSupply Corporation Television Systems Market Tracker(2)

Traditional Digital Television Functions

The digital logic requirements imposed by LCD, plasma display panel (PDP), and projection televisions are very similar. These requirements are video processing and high bandwidth chip-to-chip communication. Altera has developed and currently supports solutions for this functionality.

Traditional functions that digital television manufacturers have designed using Altera® Cyclone® FPGAs include:

• Timing controller (TCON), using proprietary customer algorithms
• Video intellectual property (IP), such as temporal or spatial dithering
• Picture quality enhancement, such as frame rate conversion and local dimming for LED back-light units
• Display interface, including next-generation protocols like V-by-One and DisplayPort

Figure 2 illustrates how these sub-functions are interrelated. 
 

Figure 2 - FPGA Implementation of TCON Function

Next-Generation Digital Television Functions

The big question for digital television is, "What is the next break-out technology?" According to Display Search, advanced technologies like LED backlights, 3D, and higher frame rates (i.e., greater than 120 MHz) will be driving explosive growth for LCD televisions over the next few years. Other factors coming into play are the on-going economic pressure to lower costs and the "green" movement towards lower power.

Altera's Cyclone series FPGAs are well suited for quickly implementing these traditional functions. Other semiconductor vendors may argue they can quickly implement these functions into new ASSPs or system-on-chip (SoC) ASICs. Digital televisions are high-volume and cost-sensitive products, but the life-cycle for each model is very short-lived. Digital television OEMs are always incorporating new features to address market trends, and today's set of next-generation features are no exception, making it hard to justify the return on investment for creating a new ASSP or SoC ASIC.

Next-generation DTV features include:

• Better resolution (i.e., 1080p to 4k2k)
• 3D
• LED backlighting
• Bigger screen sizes
• Higher frame rates (i.e., 120 MHz to 240 MHz)
• Lower costs
• Lower power consumption

Digital Television Design Challenges

How can the OEMs incorporate these new features while simultaneously tackling the everyday technical and business challenges for designing new electronic subsystems?

Some of these challenges are:

• Technical
  • Current display interfaces connecting subsystems running out of bandwidth (i.e., LVDS)
  • Choosing the best architecture for internal/external video connection; HDMI, DVI or other
  • Higher frame rates + higher resolution = faster data rates, requiring more video processing power and higher
  • bandwidth to transfer data between subsystems
  • Lowering power

Author:  Tom Schulte, Sr. Product Marketing Manager, Low Cost Products Group, Altera Corporation

Tom Schulte joined Altera in 1994 and currently works in Altera's low-cost products group as a senior marketing manager. In this capacity, Schulte is responsible for developing marketing strategies around Altera's Cyclone FPGA and MAX CPLD product families. Prior to Altera, he served as a product marketing engineer in IDT's Subsystems Division. Schulte holds a BS in Electrical Engineering from Santa Clara University.