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Viewing 1 to (7 Total) FPGA Verification |
Total Posts: 2
Joined: Jan 2010
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Hii,
While discussing FPGA based designs ,no one can ignore the importance of verification.In todays scenario verifying a design is the most challenging job.It is one of the major bottleneck in meeting the project schedules.
but can wee compromise on verification efforts?
The answer will be-NO? As an improper verification methodology will cause design re-spins,increasing the cost to market.
Now as we know there are various methods available for verifying HDL based designs.Formal verification,simulation, assertion and classical code walk through.
Which one of these can deliver.Lets discuss it here .My personal choice is assertion based verification along with transaction based test generation.
Posted on 2010-01-23 00:49:58 at 2010-01-23 00:49:58
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Total Posts: 11
Joined: Feb 2010
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Code Coverage: The First Step
I still contend that Code Coverage is the first step in putting together a cohesive FGPA simulation strategy. Without code coverage, you don't have any idea of whether your test bench is really testing the design.
While code coverage doesn't fully answer the question of whether you've tested a design, it certainly can tell you what you have NOT tested. And that's an excellent start.
Posted on 2010-02-15 22:54:32 at 2010-02-15 22:54:32
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Total Posts: 5
Joined: Feb 2010
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Requirement coverage: Second step ?
Code coverage only shows that the verification has tested statements, branches, conditions. The FPGA will never go in not stable state and definitive failure. But does it always do what it is expected to do? So for each test case, proof shall be given that the behavior of the FPGA is compliant to its specification. Of course, this is a long time to spend in modelisation or manual verification.
Posted on 2010-02-17 05:55:17 at 2010-02-17 05:55:17
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Total Posts: 2
Joined: Jan 2010
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code coverage is good! what's next
yes i do agree that code coverage is a very good start.It really gives a good estimate of the quality of the test-bench.
But to have a full functional coverage,we must have a methodology which targets the requirements.
So what are the best tools available for carrying out assertion based verification, developing layered test-benches and carrying out formal verification(!).
Posted on 2010-02-17 13:21:35 at 2010-02-17 13:21:35
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Total Posts: 5
Joined: Feb 2010
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Requirement coverage tool
Mentor ReqTracer should be a tool to manage the functional coverage. But the the video I saw of this tool did not convince me for all the functionality we needed. So we decided to develop our own tool, based on tcl scripting.
Test bench code is tagged with the requirements, the tcl script parses the test bench code to give synthesis of what is really performed in the verification simulation.
Posted on 2010-02-18 05:18:24 at 2010-02-18 05:18:24
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Total Posts: 11
Joined: Feb 2010
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Requirement Coverage Tool
Errr... Remy. Not to spew my Mentor Kool-aid all over the place, but ReqTracer does what you just said.
I suspect you saw an earlier version.
Ray "Mentor AE who drank all the Kool-aid" Salemi
PS. Why is Kool-aid spelled with an "aid" instead of an "ade" as in lemonade?
Posted on 2010-02-18 08:18:13 at 2010-02-18 08:18:13
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Total Posts: 11
Joined: Feb 2010
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The Best Tool?
I think the best tool depends up on your design and test bench.
If you have a very simple design, then you can implement functional coverage by writing down a list of tests and making sure that you've run each test. This is functional coverage.
On the other hand, if you have a very complex design, and if you're using constrained random to create your stimulus, then you'll need to implement a coverage model. This can be done with a combination of assertions and covergroups in SystemVerilog.
In that case, the best tool is a SystemVerilog simulator.
Then, after that, you can get very fancy by linking the simulator to a requirements tracking tool as Remy pointed out. At that point the best tool can be something like Reqtracer or a script like the one Remy's team created.
Posted on 2010-02-18 08:27:31 at 2010-02-18 08:27:31
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