Feature Articles
Managing Mental Myopia
Avoiding Single-issue Engineering
Altitude - 25,000 feet. Three minutes - I check my oxygen saturation - 95%. My O2 system is working with 800psi showing on the meter. I place the monitor on the shelf above the audio panel where it will wait until my next check in 3 minutes. Cylinder head temperatures - all in the green. Manifold pressure is at a turbo-boosted 29.3 inches, and fuel flow is at 17.4 gallons per hour. True airspeed shows 210 knots (241 MPH), and with the nice tailwind, we're making 276 knots (317 MPH) over the Siskiyous on our return flight from San Jose, California to Portland, Oregon. All is quiet on the radio, as we haven't seen or heard any traffic for over 20 minutes since we were transferred to Seattle Center.
At FL250 (25,000 feet above sea level) the average time of useful consciousness (TUC) is a frighteningly short 3-5 minutes. TUC is defined as the "amount of time an individual is able to perform flying duties efficiently in an environment of inadequate oxygen supply." In the Cirrus SR22 Turbo I'm flying, oxygen is supplied by a factory-installed PreciseFlight system and delivered via a full-face mask with built-in microphone. For me, as a pilot, this represents a potential hazard that I work hard to mitigate. I never venture to the flight levels (above 18,000 feet) without a co-pilot or a well-briefed passenger. If I'm distracted, somehow kink my oxygen hose and become hypoxic, my copilot/passenger is instructed to activate the autopilot to execute a rapid descent to 12,000 feet - low enough for easily breathable air and high enough to remain clear of the terrain. I also make a practice of checking my 02 saturation levels at least every three minutes. Read More
Paint-by-number ASSP
Xilinx Releases Targeted Design Platforms
If we could have our druthers, we'd like ASSPs for everything. Marketing would come in and tell us they needed a combo camera-phone-studfinder-laserlevel, and we'd say "No Problem, you'll have it by next Wednesday." Then, we'd grab our magic universal ASSP catalog, turn to page 13,562, and order up the low-power version of the CCPSLL40-LP (the 40nm low-power combo camera-phone-studfinder-laserlevel chip.) It would come with the eval board, of course, and by two hours after FedEx dropped off the package, we'd have our prototype hooked up to a CCD camera and GSM module, and we'd be e-mailing photos to ourselves (via 3G, of course) of a laser rectangle projected on the wall where the painting would hang, with the stud locations identified and overlayed for the contractor.
Now we can take the next couple of days to play golf and call marketing in on Tuesday (a day early, for good measure) for their demo.
Dawn of a New Day
SiliconBlue Shipping in Volume
Somebody said that it couldn't be done
But he with a chuckle replied
That "maybe it couldn't," but he would be one
So he buckled right in with the trace of a grin
On his face. If he worried he hid it.
He started to sing as he tackled the thing
That couldn't be done, and he did it!
- Edgar Albert Guest (1881-1959)
It is ironic that we more often hear the parody of Edgar Guest's "inspirational" poem which goes something like:
Everyone said that it couldn't be done
With a smile, he went right to it.
He tackled the thing that couldn't be done.
And sure enough, he couldn't do it.
When it comes to starting new FPGA companies, the parody is much more often the rule than the original. Numerous times over the past decade or so, we've been rustled from our sleep to hail the dawn of a new FPGA company... only to watch it waste away and die as the team struggled in vain to conquer the myriad complexities of launching a new, successful product in this challenging arena.
Embedded Display Control Applications Using FPGAs
Embedded LCD Control Applications Requirements
Graphical LCD displays are increasingly designed into demanding embedded display control and video applications such as Human Machine Interfaces (HMI) for industrial consoles, vending machines, automotive and marine dashboard clusters, household appliances, medical devices and gaming machines. A key requirement for efficient controller design is effective solution scaling as well as optimization for both cost and performance. Designers often need to integrate third-party display control solutions into their own designs, which require IP that is stable and easy to integrate with designers’ own IP modules and processor interfaces.
System designers are turning to the use of programmable logic devices such as FPGAs to implement advanced LCD graphics solutions in their designs in order to support multiple display and processor types, as well as to respond to changing market standards and requirements within a compressed window of opportunity. Following are some of the important general requirements for embedded LCD control applications, and how FPGAs excel in meeting these requirements:
A New Laser Vision
I was going to write about programming FPGAs this week, but instead, I am going to rave about a wonderful group of electronics engineers. I don’t know their names or even which the companies they work for, but they have transformed my life.
Unless you wear glasses, it is difficult to understand what a regular irritation and nuisance they are. You see the world constantly as though looking through a window, complete with a frame around it. They steam up, and in rain they make life difficult.
How do glasses play in the movies? In the classic moment in many old black and white films, the mousey little girl removes her glasses and the hero says, “Why, Miss Hackensack, you’re beautiful!” Otherwise, that’s about it.
Tunnel Vision
Engineering for Your Audience
Everyone understands that engineering is a specialty. The public is comfortable with the fact that we receive specialized training, and that gives us specialized knowledge and skills that allow us to solve specialized problems.
What the public does not understand well is that our specialty-ness is much deeper and narrower than they imagine. We've all experienced this...
"Oh, you're an electrical engineer - can you take a look at this old TV? It seems to have stopped working..."
"Well, see, I'm actually an FPGA place-and-route specialist. I develop part of the algorithm that does incremental placement of blocks when there has been just a small netlist..."
"Hey, the game is starting!"
A Parallel World
It was seven in the evening on the 5th of November, 1984, and we had almost finished copying the press pack. The launch was the next day, and I was leaving for London in half an hour, when Iann came into the room and said, “Did you know it has the power of at least a hundred of Sinclair’s home computers?”
We turned the photocopier back on, rewrote and copied the press release, and sure enough, the story that most media channels carried, including the BBC in news bulletins, was, “Inmos launches chip with the power of a hundred home computers.” While this was satisfying in its way, in the longer term it merely continued the problems with the way the product was perceived.
What we were launching was the transputer. Today it would be seen as a parallel processing tile from which to build large parallel processing systems. Then it was seen in many different ways, depending on the standpoint and knowledge of the person viewing it.
Cyclone IV
Altera's new SerDes-having Low-cost Family
This week, Altera announced their next-generation low-cost FPGA family, Cyclone IV. The new family has more capacity and lower power consumption, and, for the first time, it is available with high-speed serial IO.
[NOTE: THIS ARTICLE WILL BE CLOSED-CAPTIONED FOR FPGA GEEKS. IF YOU DON'T KNOW WHAT a "LUT" IS OR WHY "SYSTEM GATES" ARE FICTION, IGNORE THESE SUBTITLES AND JUST READ THE MAIN ARTICLE.]
Cyclone IV represents Altera's latest volley in the low-cost FPGA wars. Low-cost FPGAs have been the most competitive segment for the past several years, with Altera, Xilinx, Lattice, and Actel all fielding competent families and with the capability-per-cost of the devices out-pacing Moore's Law by a decent margin. Devices labeled "low-cost" today could compete favorably in many ways with the much more expensive "high-end" FPGA families from just a few years ago.
Once More, With Feeling
ARM and MIPS Return to FPGA?
Xilinx and Altera have each recently and respectively announced agreements with ARM and MIPS. While these announcements may be coincidental, they trigger a decade-old feeling of digital-design deja vu. A mere ten years ago, with great fanfare, Altera introduced the ill-fated Excalibur - the Titanic of FPGA families - and ushered in the era of programmable systems-on-chip with FPGAs. Like the Apple Lisa and Newton, the product itself failed, but the concept it introduced went on to flourish. Now, ten years later, that chilly feeling is back.
Before we drop too much into what we can learn from history, let's see what the companies are telling us with these announcements. The answer is... (may I have the envelope please?) virtually nothing. The announcements create far more questions than answers. Altera's response was short and sweet. They had an important customer... wait, strike that... SEVERAL important customers request the MIPS architecture, so they licensed the technology (the MIPS32 processor architecture) from MIPS. According to the MIPS press release, the agreement is "marking the entry of the MIPS® architecture into the FPGA channel." Wrong, but well-intentioned (but we'll get to that later).
FPGA IP: Keeping Your Device Options Open
The use of third-party intellectual property (IP) is all but a necessity for most FPGA designs today. The complexity of platform designs as symbolized in Figure 1, the sophistication of modern FPGA architectures, and time-to-market pressures combine to force engineers to call on proven IP elements for at least some the standard functionality within their emerging designs. They rely on IP ranging from storage elements and arithmetic cores to system-level IP offering broader functionality including processors, interfaces, peripherals, and more.
The design challenge is twofold: first, to use these types of IP effectively for the current project; and secondly, to re-use them with similar effectiveness in future projects even if the target device changes. A design team has to think about more than just one upcoming product roll-out. What about the second and third versions, with their inevitable need for new and improved capabilities? To retain its competitiveness, a system house needs to capitalize on the competitiveness of the whole FPGA vendor market, where vendors continually leapfrog each other with the biggest, fastest, cheapest, or most power-efficient devices. It’s a buyer’s market. The reason for switching devices may be technical, economic, or something as simple as the valued business relationship with an FPGA vendor or distribution partner. By being able to re-target the same design to another device with minimal effort, a design team can select the best silicon for each successive project. This degree of portability requires a device-neutral design methodology—and if a single FPGA vendor’s proprietary IP is richly used, this can get complicated.