Feature Articles
Graphic Composition
I never thought I would be able to quote Karl Marx, the bearded philosopher, historian, revolutionary, and founder of communism, in an article on FPGAs, but here we go. “History repeats itself, first as tragedy, second as farce.”
What I am thinking about is the way in which we design components. With ASICs and SoCs, we have seen a steady progression of increased abstraction in the EDA tools, from drawing the individual transistors as rectangles in the layers of silicon, up through schematic entry, through hardware description languages, to the emergence of today’s work on tools that describe entire systems. ESL (Electronic System Level) design is a good buzzword here, and we are seeing a lot of tools (plus a lot of smoke and mirrors) emerging in this domain. Tragedy is perhaps a harsh word to describe the evolution of these tools, but there haven’t been a lot of laughs in trying to ride Moore’s Law as process nodes get smaller and smaller and re-spins escalate into the stratosphere. Read More
Changes in the Wind
Altera Shows 28nm Plans
We like our pictures.
We like them to move and we like them to be sharp.
We also want them in our pockets.
Delivering high-quality video to mobile devices is truly a system-wide endeavor. Every link of the chain - from the heavy-iron infrastructure to the wireless access points to the mobile devices themselves require a major upgrade in bandwidth, compute performance, quality of service, and power efficiency. If you take your favorite market forecast and a spreadsheet, you can start with the number of subscribers and do the math back through the system - and come up with some sobering figures for bandwidth at every level. Today's 40G/100G challenges become tomorrows 400G challenges – and, with specifications and standards guaranteed to be in flux, this spells a big opportunity for programmable logic devices.
Fending Off Evil
Protecting Your FPGA Against DPA
It's 3AM, and you wake unexpectedly. They're out there... the Evildoers. You can almost feel them. They're out there right now holding a copy of your latest board - with the FPGA sitting right in the middle. It's the same one you put in your design. Reverse-engineering the board is easy - or heck, they may just have a way to sneak a few off the assembly line where they're being made. You know the place - you were nervous when purchasing made the deal. The prices were a little too low and the opacity was a bit too high. That's why you have it set up so your FPGA bitstream doesn't get loaded until the product gets back to your facility.
Nonetheless, they're out there. They're looking at your board right now, and they're trying to figure out how they can steal your design - or your customers' data. You took precautions, of course. Maybe your bitstream is encrypted with the FPGA-vendor's security features. Your customers' data is definitely encrypted. You can go back to sleep now, right? They won't be able to get your encryption keys.
A Perfect DSP Storm
BDTi + High Level Synthesis + FPGA
For years, we've discussed how, for high-performance algorithmic design, FPGAs are capable of performance, efficiency, and cost-effectiveness orders of magnitude better than alternative solutions like DSP processors*. There! Did you see that? The asterisk? You know what that means. Somewhere, down the page, hidden in the fine print at the bottom is the caveat. This time, however, we won't bury the caveat. We'll pull it up in plain view, attack it, and make it go away permanently... well, almost.
For years, we've also discussed how, for algorithmic design, high-level synthesis tools (HLS) can take your C or C++ algorithm and automatically create optimized, parallelized hardware implementations that approach the quality of hand-coded RTL*. Yep, another asterisk. We'll tackle that one too.
From Pinout to Layout:
The FPGA/PCB Balancing Act
When a fifth of all designers say board integration is the biggest trouble spot in getting their product out the door , one has to conclude that the FPGA/PCB co-design dilemma remains unsolved for many. Either the FPGA designers continue to make pin assignments that simplify their own design closure goals but complicate those in the PCB domain, or the PCB team locks down pins early in the design cycle only to complicate design closure in the FPGA domain.
Though technology solutions have been available to facilitate pin assignment closure, bridging the FPGA and PCB gap requires collaborative techniques that do not demand that teams adopt new design behaviors. To minimize the iterative process from impacting time-to-market goals and risking product revenue, technologies need to be enhanced in multiple areas of the flow.
FPGAs and the New IP Economy
Micro-scale Hardware as a Service
As engineers, all of us probably had to take at least one economics course in college. It was usually one of those curriculum "requirements" that we agonized through, amused only by the discovery that Laplace transforms were useful for something besides jumping between frequency and time domains.
(If you're one of our few non-engineers, don't let that last line scare you away. We're going to be talking about economics here - supply and demand and competition and giving stuff away for free and the system collapsing in on itself and leaving us in poverty after agonizing years of ... Oh, sorry. Got carried away there.)
Timing Closure Methodology for Advanced FPGA Designs
Today’s design application and performance requirements are more challenging due to increased complexity. When performance requirements for any part of a design are not completely satisfied, the system fails to function as desired. Whether using application specific standard products (ASSPs), application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs), timing closure poses a challenge for system design.
What Makes a Design Complex?
In the design process, several factors can make timing closure difficult to achieve. For example, in FPGA designs, resource location can be a concern. Locations of specialty blocks, such as DSP, transceivers or RAMs can pose problems as a result of congestion around these blocks. Poor resource placement can result in unmet timing requirements.
A Mighty Wind of Programmability
Moshe and Krishna Talk About Xilinx, FPGAs, and the Future
Kevin Morris (Editor, FPGA Journal): We did an interview two years ago when you first started as CEO of Xilinx. How have the first 2 years gone?
Moshe Gavrielov (President and CEO, Xilinx): It's been a blast. I joined because I felt that everything was going toward programmables, and that feeling has just been reinforced the past 2 years. Now, I believe we have reached a threshold where it is going to accelerate. Of course, I'm sure you have heard this from many frothy FPGA CEOs over the years before, and the question is what's different now? To be perfectly honest, I feel like the message of FPGAs was oversold. Primarily, there were other alternatives, and FPGAs were not quite there in a whole host of ways. What's happening now is that the other alternatives are quickly disappearing. The demise of ASIC has been well documented, and there's a lot of data to support that, but now a similar thing is happening with ASSPs.
As the semiconductor industry was maturing, there was a huge influx of money coming into the semiconductor world through government, venture capitalists (VCs), and the stock market. But, if you look at what has happened over the past 10 years, the return on those investments has been terrible, and therefore there is now much less money coming in. I think that trend is not going to reverse itself, because the VC world has gone through its own crisis. They have not seen positive return, so they're actually seeing their partners [Limited Partners - LPs] investing a lot less. One critical thing that the LPs discovered during the last downturn is that, since you invest 10 years at a time and you are committed for a certain period of time, there is absolutely zero liquidity. Investors are now recognizing that liquidity is important. Not only could they not pull money out of a commitment, they still had to continue to fund. If you commit a certain amount of money and you've paid a portion, that money is still on call, and you end up sending more money in to protect your previous investment when you'd really rather be pulling money out.
Managing Mental Myopia
Avoiding Single-issue Engineering
Altitude - 25,000 feet. Three minutes - I check my oxygen saturation - 95%. My O2 system is working with 800psi showing on the meter. I place the monitor on the shelf above the audio panel where it will wait until my next check in 3 minutes. Cylinder head temperatures - all in the green. Manifold pressure is at a turbo-boosted 29.3 inches, and fuel flow is at 17.4 gallons per hour. True airspeed shows 210 knots (241 MPH), and with the nice tailwind, we're making 276 knots (317 MPH) over the Siskiyous on our return flight from San Jose, California to Portland, Oregon. All is quiet on the radio, as we haven't seen or heard any traffic for over 20 minutes since we were transferred to Seattle Center.
At FL250 (25,000 feet above sea level) the average time of useful consciousness (TUC) is a frighteningly short 3-5 minutes. TUC is defined as the "amount of time an individual is able to perform flying duties efficiently in an environment of inadequate oxygen supply." In the Cirrus SR22 Turbo I'm flying, oxygen is supplied by a factory-installed PreciseFlight system and delivered via a full-face mask with built-in microphone. For me, as a pilot, this represents a potential hazard that I work hard to mitigate. I never venture to the flight levels (above 18,000 feet) without a co-pilot or a well-briefed passenger. If I'm distracted, somehow kink my oxygen hose and become hypoxic, my copilot/passenger is instructed to activate the autopilot to execute a rapid descent to 12,000 feet - low enough for easily breathable air and high enough to remain clear of the terrain. I also make a practice of checking my 02 saturation levels at least every three minutes.
Paint-by-number ASSP
Xilinx Releases Targeted Design Platforms
If we could have our druthers, we'd like ASSPs for everything. Marketing would come in and tell us they needed a combo camera-phone-studfinder-laserlevel, and we'd say "No Problem, you'll have it by next Wednesday." Then, we'd grab our magic universal ASSP catalog, turn to page 13,562, and order up the low-power version of the CCPSLL40-LP (the 40nm low-power combo camera-phone-studfinder-laserlevel chip.) It would come with the eval board, of course, and by two hours after FedEx dropped off the package, we'd have our prototype hooked up to a CCD camera and GSM module, and we'd be e-mailing photos to ourselves (via 3G, of course) of a laser rectangle projected on the wall where the painting would hang, with the stud locations identified and overlayed for the contractor.
Now we can take the next couple of days to play golf and call marketing in on Tuesday (a day early, for good measure) for their demo.