A New Way to Design FPGAs

FPGAs have proven to be a viable solution for a broad range of applications, from early beginnings in telecommunications, to the highly complex computing systems of today.  In fact, the FPGA industry is seeing more complex designs than ever before—with the demand for larger and faster FPGAs to create innovative end-products.  With the sheer number of FPGA resources, the availability of more sophisticated EDA tools and the SystemVerilog language, new process flows for ESL design, and the strengths or limitations of the design team, FPGA designers are faced with lots of choices when developing their new technologies.  The customer must often negotiate getting the best unit cost from the FPGA vendor, since price sensitivity is crucial in many markets. In addition, the importance of getting these products out the door on-time, within tighter budget and resource constraints, has become even more challenging in the highly competitive FPGA based system markets. 

While we value our relationships with the FPGA vendors, like Xilinx and Altera, we also  need to address the free design tools these vendors provide the customer.  Free tools promote and drive the use of vendor-specific IP, and since up to 80 percent of all designs are reused today, this is significant.  However, if the designs are captured using vendor-specific tools, and if the customer needs to redesign or retarget that design to different IP providers, they may be challenged in reusing this design.  Therefore, vendor independence is crucial for today’s FPGA design applications.  We need a solution that allows the customer to capture and reuse designs with flexibility, portability and reliability.  In doing so, the designer can retarget his designs to different providers, and even to different silicon platforms, for optimum productivity.

Also, according to Gartner’s EDA study in 2005, 51 percent of all ASIC designs are verified using FPGAs.  What’s needed are tools that specifically address and support ASIC prototyping since reliance on the vendors’ tools can often result in project delays and unsatisfactory attempts to verify these complex designs.  Essentially, the message is quite simple:  current technologies and methodologies are insufficient for addressing today’s FPGA design challenges.  So what is forseen as a better solution?

We need a solution that can greatly improve productivity and resources used by FPGA designers today; a solution that is easy-to-learn and implement, yet more sophisticated than the vendor “freeware” that’s readily available today.  I see several challenges that the design teams face—the need for better synthesis that is not vendor-dependent, but improves design performance for a broad range of devices from multiple vendors.  And a solution that supports new standards like SystemVerilog, or applications such as ASIC prototyping with superior gated clock conversion capabilities.

We also need a solution that can significantly reduce design iteration time while effectively processing last-minute cycle changes.  If the designer is able to recompile and synthesize only small sections of the design that have been changed, this could be a significant time and cost savings.  Likewise, a better solution for place and route, and flexibility with partitioning the design is needed. 

From discussions with customers, designers want and need to make “what if?” tradeoffs to optimize their designs for performance or area—they would like to easily identify available architectural blocks and re-map implementations for best performance and device implementation.  As of today, there is no such comprehensive solution, but our goal as a business and technology leaders in the EDA industry is to continue listening to customers and vendor partners and help evolve our technologies to meet these needs.  If we can develop a solution that can support these key areas, the FPGA design community can design more innovative products with great productivity, profitability and gain a competitive advantage.   That’s a vision everyone should care about.

by Simon Bloch, general manager, Design and Synthesis Division, Mentor Graphics Corporation

September 11, 2007

Author’s Bio:
Simon Bloch has served as general manager of the Design and Synthesis Division at Mentor Graphics since 2002. He is responsible for design and synthesis products for HDL and ESL. Prior to Mentor he held senior management positions at Aristo Technology, Compass Design, VLSI Technology and Daisy Systems working on IC design technologies in the front end and physical flows. Prior to EDA he designed ASICs and systems in telecommunication applications. Bloch has a BSEE from Tel Aviv University majoring in microelectronics, computers, and medical engineering.

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