Flash Flood
Inside FPGAs' Non-volatile Companions

For many of us in the FPGA world, flash is one of those technologies we tend to take for granted.  “Yeah, and we’ll just throw some commodity flash in there for configuration and stuff.”  With little fanfare, we throw down some device and hook it up like the datasheet says, or like it was hooked up on the development board, and give it very little thought after that.  The thing is, flash is an incredibly versatile and dynamic technology, and understanding it can help us make better design decisions that can dramatically improve (and sometimes save) our development projects.

Last week, the second annual Flash Memory Summit took place in Santa Clara, CA.  FPGA Journal dropped in on the event in an effort to learn more about the latest trends in the volatile world of non-volatile memory.  We found a tremendous amount of energy as well as a great deal of confusion and controversy surrounding our little double-gated buddies. 

Flash memory has been with us since 1984 when Toshiba’s Fujio Masuoka announced the invention the first flash technology.  The name “flash” was appended to the EEPROM technology after a colleague suggested that the process for erasing the devices was similar to a camera flash.  There are two primary types of flash on the market today.  NOR flash (which gained popularity early due to the full random-access address/data bus structure) and NAND flash (which is more recently popular because of its much higher densities, longer life, and lower cost).

NOR flash structure is like a mutated MOSFET with two gates.  Dr. Masuoka didn’t just have one of those horror movie lab accidents, however.  This double-gating has a purpose.  The first gate is called a “control gate,” and the second is a “floating gate.”  The floating gate is insulated on all sides by an oxide layer.  It is the Roach Motel for electrons.  Once we check some in (by a process called hot-carrier injection), they can’t check out.  The charge on the floating gate affects the current flow on the control gate. By applying a voltage to the control gate, we can detect the level of charge on the floating gate.  This is how a NOR flash cell is read. 

In fancier, multi-level cell implementations, varying degrees of charge can be applied to the floating gate, and varying levels can be read back, allowing storage of more values than just a “1” or “0” and increasing the effective storage density.  This is for advanced students only, however, and the mechanics of multi-level cells are beyond the scope of our discussion here.

When NOR flash is in its “erased” state, all cells have a logic value of “1”.  Current will flow through the channel when voltage is applied to the control gate.  “Programming” a bit of NOR flash sets the value to “0” by the aforementioned “hot-carrier injection” or “hot-electron injection” process.  A higher voltage is applied to the control gate while the channel is turned on.  The current through the channel spikes and causes electrons to jump through the oxide layer into the floating gate where they’re stuck – kinda’ like roaches in one of those cardboard fly-paper traps.

Also like roach traps, it is considerably harder to get the electrons out of the floating gate than into it.  A much larger voltage must be applied from the control gate to the drain (with the polarity switched, of course).  This vacuums the extra electrons off the floating gate by a process known as “quantum tunneling.”  Feeling smarter now?  Don’t rush to the break room just yet.  There’s more.  Modern NOR flash is erased an entire block at a time, making some additional intelligence necessary when trying to use it as a general-purpose non-volatile media.  The fast-and-easy-to-read, slow-and-difficult-to-write properties of NOR flash has made it an ideal re-writable substitute for ROM in many systems – particularly including applications that need program storage.

NOR flash is so-named because of the topology of the cells – they resemble the structure of a NOR gate.  Obviously, however, there are plenty of good reasons we might want to use flash to replace parts of our system other than ROM.  A solid-state substitute for hard drives as mass storage might be a good example.  Of course, to offer any alternative to hard disks on a cost basis, the price per bit of flash had to be dramatically reduced.  This is where NAND flash comes in.  By streamlining the architecture and eliminating lots of the address logic, much higher densities could be realized.  NAND flash reads and writes more like a disk drive than a ROM.  Reads and writes are done in pages, and data is streamed out serially.  Erasure is done in multi-page blocks. 

Also like disk drives, NAND flash includes (or requires) error detection and correction logic, as well as logic to manage bad blocks.  As flash cells have a finite number of write/erase cycles, logic is required that can do load leveling – attempting to equalize the number of erasures across the device rather than putting all the stress on the early addresses.  This leveling, bad block management, and error correction can dramatically increase the useful life of a device (as well as the yield of devices on the line).  Because of these techniques (and because of the difference in the physics of the programming and erasure process), NAND flash has a much longer lifespan than NOR flash, making it more suitable for applications where longevity is critical.  In most modern systems, the longevity of NAND flash (up to a million cycles) provides far more than the life expectancy of the system in the field.

Because NAND flash isn’t randomly readable like NOR flash, it can’t be used directly for program memory storage.  Instead, a strategy that resembles virtual memory management is used.  A smaller RAM cache holds the working program, and new data is paged in from NAND flash as needed.  This compromise makes NAND flash awkward for program storage, but still very good for applications where it is replacing traditional mass storage devices such as hard disks. 

Of course, all this complexity in NAND management leads to proprietary idiosyncrasies in NAND flash devices.  Designing one NAND flash into your system doesn’t mean that you can easily swap in devices from another vendor – an important consideration if you are worried about your supply chain.  The Open NAND Flash Interface working group (ONFI) is working on addressing this issue by creating a standard (ONFI version 1.0 is the current incarnation) for physical and logical interfaces to NAND flash devices.  Major flash manufacturers are collaborating on implementation of the ONFI standards, so you can probably have multi-vendor NAND flash supplies for your system as long as you don’t try to color too far outside the lines.

In the FPGA world, we encounter flash in many incarnations.  Flash is one of the most popular means for external storage of FPGA configuration data.  The NAND flash architecture works great for streaming in the configuration bitstream and occasionally re-writing with an updated configuration.  Following on that idea, Xilinx has created virtual non-volatile FPGAs by die-stacking commodity flash on top of a Spartan-3 FPGA.  Lattice Semiconductor has created non-volatile FPGAs by including flash memory directly on the FPGA die itself, allowing on-chip reconfiguration of the SRAM configuration logic.  Actel has ventured the farthest into flash integration with their ProASIC3 and Fusion product lines, which use flash cells in the actual FPGA configuration logic – making an FPGA that holds its configuration even through power-off cycles. 

One of the big questions in the flash world is whether flash (or any solid-state non-volatile storage) will ever replace hard disks.  Currently, hard disks have a huge cost advantage, but flash is gaining some ground.  Every time we’re tempted to chime in with a “flash will never catch up because of hard disks’ 100x cost advantage” claim, we’re reminded of Bill Gates’s supposed “you will never need more than 640K of main memory” quote, and so we keep our silence.  Either way, when designing a variety of applications where FPGAs are involved – where rugged, low-power, high-density, non-volatile storage is required – a working knowledge of flash technology can be an important asset.

August 14, 2007

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