FPGAs and Ethernet
Providing Programmability to Pervasive Interconnect Standard

Ethernet is the most widely used connectivity technology today. Previously limited to WAN and LAN, Ethernet is now making inroads into industrial, medical, video, aerospace and defense markets. Ethernet can be used not just for the data path but also on the control plane for applications, such as system management, remote monitoring and debug. Ethernet usage is predicted to rise rapidly in the coming years (Figure-1: Escalating Ethernet Use). While Ethernet specification defines several speeds from 10 Mbps to 10 Gbps, the fastest growing segment is Gigabit Ethernet, mainly due to migration of desktop connectivity from 100 Mbps fast Ethernet. Embedded designs, however, will continue to use connections at 10/100 Mbps speeds. 10 Gbps Ethernet is typically restricted to high-end bandwidth applications, such as multi-gigabit serial backplanes and fat data pipes.

Figure-1: Escalating Ethernet Use

Another reason to use Ethernet in the embedded space is its interoperability, especially as a system typically uses two to three devices from different vendors. An interface that cannot guarantee interoperability between two vendors’ devices is not practical and a limitation for most engineers. By following the specification, most vendors make sure that the implementations are compliant. On top of it, they run their Ethernet devices through industry standard Ethernet interoperability test programs offered by independent laboratories, such as University of New Hampshire’s Interoperability lab (UNH IOL). A device that successfully completes the UNH IOL program is considered certified for interoperability. 

As Ethernet moves from traditional networking applications to embedded applications, it has become an essential connectivity standard for FPGAs – the most widely used chips to build custom logic for embedded systems. A major reason is that the Ethernet specification only defines Layer one and two in the network topology. This leaves the top five layers in the seven-layer Open Systems Interconnection (OSI) network model (Figure–2: Ethernet in the OSI Network Model) to be implemented, as per the end application requirements. In addition, embedded designs are typically low- to mid-volume applications, which means ASIC/ASSP implementations are likely expensive and less preferred. FPGAs – due to their high performance, flexibility, scalability, low-development cost and protection against obsolescence – offer an ideal solution.

Figure 2: Ethernet in the OSI Network Model

Historically, FPGAs were primarily used to bridge between Ethernet and other protocols within the system. The most obvious method used FPGA with external MAC/PHY chips. As FPGA fabric performance started improving, designers started integrating MACs within the FPGA logic in order to achieve better performance. The next logical step for FPGA vendors was to embed hard IP blocks within the FPGA fabric. For example, Xilinx initially added hardened tri-mode (10/100/1000 Mbps) Ethernet MACs to its Virtex-4 FPGAs. The MACs in the latest Virtex-5 FPGAs not only support more features but also have successfully completed the UNH IOL test program (Figure-3: Virtex-5 Hard Ethernet MAC).

Figure 3: Virtex-5 Hard Ethernet MAC

A hardened MAC within the FPGA saves logic resources compared to a soft-core implementation (e.g., ~3600 LUTs in a FPGA device). This may allow you to choose a smaller device and save power. In addition, you also reduce the number of external components on board and use fewer FPGA pins for Ethernet connectivity. The development process becomes easier and shorter.

Moreover, with the ability of FPGAs to implement processing functions (DSP/MPU) using hard/soft IP cores is giving rise to system performance, previously only possible with ASICs. While DSPs and MPUs with Ethernet ports have been shipping for a while and are inherently programmable, conventional systems built using these processing engines are still overwhelmed when faced with high-frequency I/O operations. FPGA-based platforms can provide the needed hardware acceleration to solve the processing bottlenecks and provide extra flexibility in comparison to ASIC implementations. When you look at all the pieces of the puzzle – abundant logic resources, hard/soft Ethernet MACs, on- and off-chip memory, hard/soft processing cores, DSP blocks, high-speed I/Os and specialized routing within the FPGA – it becomes clear that designers now have an option to build fast, customized functions using off-the-shelf chips.

Below are some of the emerging applications that necessitate the use of FPGA’s processing power and Ethernet connectivity.

Industrial Ethernet

Ethernet’s dual advantages of treating every data acquisition node as an IP address or Web page, as well as its longer reach and higher data rate, make it an ideal industrial networking solution. Ethernet, alone, cannot handle real-time data transfer. However, combining Ethernet with a higher-level protocol, such as IEEE 1588 based on User Datagram Protocol (UDP), reduces network synchronization down to a microsecond.

Such networks are often custom built for a particular setup, making FPGAs the ideal development platform. Figure-4 shows a typical implementation of an industrial network using Ethernet and IEEE 1588. The FPGA device generates IEEE 1588 precision time protocol (PTP) packets based on IP multicasting. It then timestamps them and sends them to a network switch. The switching function could be implemented in the FPGA itself if the number of required nodes is not too large.

Figure 4: Industrial Network with Ethernet and IEEE 1588

Network Test and Instrumentation

When evaluating network equipment before deployment in a complex network infrastructure, it is generally not advisable to use the real network itself, as delays and uncertainties can give unpredictable results. In addition, network testing during development may give poor Quality of Service (QoS) to network clients. FPGA-based, fully programmable network test-beds that provide functions – such as WAN emulation, network instrumentation, traffic shaping, network monitoring and traffic generation at wire speeds – are preferred.

By using an FPGA, the user can change functionality based on what he/she wants to measure. Figure-5 shows the block diagram of a programmable network tester with four Gigabit Ethernet ports connected to an FPGA. Inside the FPGA are four GbE MACs, FIFOs, memory controllers and logic used to perform desired network functions. Off-chip memory, capable of reading and writing Gigabit Ethernet packets simultaneously, is used.

Figure 5: Programmable Network Tester

IP-based surveillance system

The latest generation of video surveillance systems use digital LAN cameras, complex image processing and video-over-IP routing to capture, store and transmit crystal clear streams. Images are pre- and post-processed to enhance picture quality in real time with low latency and then transported over a video stream using various encoding and decoding standards (CODECs). The data has to be compressed as the stream size and rate is high. For example, a transmission at 640x480 pixels at 30 frames/second requires 26 Mbps uncompressed.

FPGA devices containing embedded DSP blocks, on- and off-chip memories and Ethernet Connectivity are the ideal chips to build such systems. Figure-6 shows the block diagram of a digital IP based surveillance system. The FPGA reads the data presented by an NTSC/PAL decoder and then pre-processes it. A CODEC such as H.264 is used to compress the data. The data is then converted into Ethernet packets with the appropriate header information for decoding at the receiving end and finally sent over Ethernet links using a MAC.

Figure 6: IP Based Surveillance System

Data Acquisition System

Radar, cosmic radiation measurement and astronomical observation applications require large data acquisition systems with many sensor channels. For example, weather radar transmits radio frequency signals and acquires meteorological information based on the echo of such signals from particles in the atmosphere. Data acquisition systems must process the raw data and it turn into a meaningful format. Since physical access to such systems is restricted, remote reconfiguration capabilities are needed to meet various user requirements. Many times, data from multiple systems is processed together to get a clear macro picture.

The remote configuration, connectivity and low-volume requirements of such systems make FPGAs ideal platforms for implementation. Figure-7 shows the block diagram of a data acquisition system used for weather radar applications. Data from sensors is read out by the FPGA. Embedded processors, DSP blocks and logic within the FPGA then process the data and send it on to a higher level control entity using Ethernet network/fabric. External memory is used to process large amounts of data efficiently.

Figure 7: Data Acquisition System for Weather Radar

Summary

A combination of Ethernet connectivity and high performance FPGAs is changing the embedded system design landscape.  The latest FPGA devices on the market now offer up to four hardened tri-mode Ethernet MACs immersed in the FPGA fabric. These devices offer the user unparalleled levels of integration and performance. Increased performance means the designer can now implement his/her design using custom programmable logic and significantly reduce development costs (ASIC NRE and tools). As FPGAs move further along the ever-shrinking process geometry path, it is likely that designers will continue reaping the benefits of falling Ethernet and device prices even for small- to mid-volume applications.

by Navneet Rao, Technical Marketing Manager, Platform Solutions
Xilinx, Inc.

July 10, 2007

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