Platform's Promise
Design Tools of the Future - Today

My kids were prodigious overachievers all the way through high school, and I’ve always been very proud of them. However, there’s a different kind of feeling you get if one of your children follows in your own footsteps, accomplishing something you also were motivated to achieve. I studied electrical engineering in college because I wanted to design computers. I had been fascinated by the potential of programmable systems from an early age, and I worked hard to hone my skills and to build expertise in the challenging discipline. In the course of my schooling, I learned that most computers follow the same basic architecture, and that the process of computer system design is usually a series of decisions about which particular components – processors, peripherals, memory, bus structure - best fit the requirements of your project.

Last week, my daughter finished the design of her first computer system. She selected a processor with enough performance, but kept the cost and power consumption in check. She struggled for awhile over bus speeds and RAM configuration, finally choosing a setup with more memory than she thought she needed operating at a frighteningly fast clock rate. She fiddled with a few power options before selecting a scheme that seemed adequate, then began choosing peripherals that were specific to her intended applications. Her O/S decision had already been made except for a few details, and most of the applications software that would be running on the system had already been designed in advance.

She is now done with her design process and is in that anxious and uncomfortable waiting process, hoping everything is goes as she expects during manufacturing. I can sympathize with that feeling. Perhaps most of us in engineering have been there ourselves.

I was struck by how simple and straightforward the process was compared to what I would have gone through trying to produce a comparable system in my day, and I realized that the combination of her chosen platform design tool and a wealth of pre-verified modules connected over standard interfaces had truly delivered her to the promised land of platform design based in IP assembly. Many have said that platform design tools are little more than demo-ware, and that design by IP assembly will never allow the masses to design complex computing systems with a few mouse clicks without ever writing a line of HDL.

My daughter is about to prove them wrong.

When her new laptop arrives from dell.com, she will have shown that a 16-year-old theater major with very little computer design knowledge can navigate a complex set of design tradeoffs, creating a customized computing platform tuned for a specific set of requirements and trading off parameters like cost, power, performance, feature set, and software. Her system design will have been completed in less than a day, and her system will be back from manufacturing in less than two weeks. Let the naysayers behold!

The key is a cleverly configured platform design tool, an effective IP testing and delivery mechanism, and pre-tested compatibility between IP blocks and standardized switching fabrics. The same strategy that my daughter used so effectively on dell.com is being deployed today for a much more demanding and technically-savvy audience by EDA, FPGA, and ASIC companies. While these systems still have their limitations, the promise of productivity acceleration by rapid IP assembly is here today.

In the FPGA space, Altera has been the trailblazer on platform-based design. Their SoPC Builder, launched a few years ago as a delivery package for their original Nios soft-core processor, has grown and evolved into a general-purpose (for Altera FPGAs and structured ASICs) IP delivery and platform assembly system. “We saw the value in a standardized approach to IP delivery, and SoPC Builder made an excellent product to build our IP integration strategy,” Says Chris Balough, director of software and Nios marketing at Altera. SoPC builder includes a comprehensive licensing system complete with a “try before you buy” feature that allows designers to preview IP blocks in their design before committing to a purchase from a third-party supplier. SoPC Builder is a standard component of Altera’s Quartus II design environment.

Xilinx supports their embedded PowerPC and proprietary MicroBlaze soft-processor with their Embedded Development Kit (EDK) and Platform Studio. The EDK includes platform assembly and software development and debug tools. The system supports Xilinx processors as well as the entire range of processor-compatible Xilinx FPGAs.

Actel has announced plans to join the platform assembly race as well, with a major upgrade to their Libero tool suite accompanying their upcoming Fusion mixed-signal FPGA family. The Fusion series is slated to support an ARM7 soft-core processor and some soft peripherals in its flash-based FPGA fabric. Fusion will also have some hard-wired peripherals for platform implementation as well as programmable analog components. The new design software capabilities are intended to simplify the process of platform design with the new family, making the technology useful to a much wider audience.

Beyond the FPGA vendors, the EDA industry has been busy at work bringing platform assembly to reality as well. Altium’s multi-FPGA-vendor Altium Designer/Nexar suite has always used an IP assembly methodology based on a board-level design style with a rich component/IP library aimed at easing the transition of board-based systems designers into platform design with FPGAs. Altium’s system includes a set of vendor-independent development boards that allow swapping of FPGAs from different vendors using plug-in modules. Altium also offers their own soft-core processors that are compatible with various vendors’ FPGA technologies, allowing truly technology-independent FPGA-based platform design.

Mentor Graphics deploys their Platform Express product primarily in ASIC/COT design scenarios, but sees significant use in FPGA teams as well, particularly when a design methodology uses FPGAs for ASIC/SoC prototyping or verification. Platform Express supports a variety of interconnect and bus standards for assembly of embedded platforms based on a large IP base. Mentor also participates in the SPIRIT consortium which is working to create standardized means of IP interchange and interconnect. SPIRIT is working to promote IP interoperability between automated tools by defining a standard for IP meta-data description, and an API for IP tool integration. Like most standards efforts, the idea is that a unified standard will benefit all participants by creating a more robust market for both tools and interchangeable IP.

Accelerated Technology, another division at Mentor, brings the embedded software expertise of their division into the platform assembly picture. Many IP blocks, such as Ethernet, for example, also require middleware components to make the hardware IP available for programming access through the RTOS. Accelerated Technology has also worked to make their Nucleus RTOS automatically configurable for platforms created through Platform Express as well as FPGA-vendor supplied tools, minimizing the engineering effort required to get an entire RTOS-supported embedded platform up and running. “We are seeing considerable demand for FPGA-based use of our Nucleus operating system,” says Robert Day, Director of Marketing at Accelerated Technology. “As a result, we’ve been working very closely with FPGA companies to support their processors and design flows with our RTOS, middleware, software IP, and embedded development tools.

Led by The Mathworks, digital signal processing (DSP) design is also following a path toward IP assembly for rapid implementation. The Mathworks has always been a favorite among DSP algorithm developers with their Matlab mathematical modeling tool. As adoption of Matlab for DSP design became almost universal, the company created their now-popular Simulink product aimed directly at the digital signal processing and control system design market. Simulink allows IP-based assembly of DSP implementations from standardized components supplied in a function library. A number of FPGA/DSP design tools such as Synplicity’s Synplify DSP, Altera’s DSP Builder, and Xilinx’s System Generator for DSP support specialized IP libraries with direct implementation capability that partially mirror the Simulink library. Once a DSP design has been assembled (and usually converted from floating- to fixed-point within Simulink), the technology-specific components are substituted for the Simulink components, and the design can then be taken directly to implementation through conventional synthesis and place-and-route.

In most cases, however, a smooth highway from platform-assembly system design to DSP-assembly design of signal processing components is not yet complete. DSP components may be designed with the IP assembly methodology, and the primary processor-based system may also be created with platform assembly tools, but the final connection of those two worlds takes place in the traditional synthesis/place-and-route domain.

Juergen Jaeger, Director of Marketing for Mentor Graphics FPGA business unit, cautions that traditional FPGA designers may be dissatisfied with the results of platform-based design as it stands today. “Often the design that comes from the IP assembly method is wasteful in terms of performance and area. In particular, FPGAs don’t have a lot of extra density or performance available, so many people still need to use traditional HDL-based synthesis and place-and-route optimization to get performance and density results they’re happy with. Otherwise, they may not be able to complete their design, or they may spend a lot of extra money on the FPGA because they have to get a bigger part or a faster speed grade.”

Even though the methodology is not yet perfect, platform assembly is clearly headed toward the mainstream in terms of design methodology. When it’s there, the ability to quickly create a sophisticated, custom embedded computing system with programmable logic will be available to a vast new market that did not previously have a way to take advantage of the capabilities of FPGAs. FPGA and EDA vendors know this, of course, which is why they’re working so diligently to prove and optimize the platform assembly process. For my part, when my daughter’s new laptop arrives next week and she powers it up and goes to work, I’ll be a believer.

Kevin Morris, FPGA and Programmable Logic Journal

August 9, 2005

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