A Wolf in Sheep's Clothing
Altera Introduces MAX II

In 1967 Andy Granatelli showed up at the Indianapolis 500 with a different kind of race car. Instead of the usual shriek of a high-performance racing engine, the car flew past the grandstands with a quiet “whoosh”. It was faster than the other entries at the race that year – much faster. The turbine-engine car had a tremendous advantage over its reciprocating-engine rivals. Parnelli Jones drove the car in the lead for 171 laps before a simple bearing failure took it out of the competition.

The question immediately arose: Is this really a race car? By jumping to a design that was more akin to a jet engine than a traditional racing powerplant, Granatelli had challenged the status quo by attacking the common notion of the underlying engineering architecture.

Just over a decade later, in 1988, Dennis Conner showed up at the America’s Cup challenge with a different kind of America’s Cup yacht. Instead of the usual graceful monohull design with billowing sails, Conner’s boat was a high-tech catamaran design, comprised of two parallel streamlined hulls powered by a vertical wing-like airfoil. His Stars and Stripes catamaran beat challenger New Zealand by two of the widest margins ever recorded in the event.

The question arose before the race ever began: Is this really an America’s Cup yacht? In responding to an unexpected challenge, Conner had also challenged the status quo by attacking the common notion of the design.

About 16 years later, (this week, in fact) Altera announced MAX II, a new super-low- cost, low-power CPLD. Instead of the usual PAL-like macrocells arrayed on the CPLD architecture, MAX II has something no one expected: look-up tables (LUTs). This is a different kind of CPLD with higher density, lower dynamic power, and higher performance than existing CPLD families.

The question arises immediately: Is this really a CPLD? By choosing an LUT-based architecture for its new CPLD, Altera is following in the footsteps of Granatelli and Conner. They are bringing a gun to a knife fight. Everything about the externals of this device says CPLD: the name, the design tools, the price… even the size, which almost doubles the previous CPLD high-water mark, is still given in “equivalent macrocells”.

With a nod and a wink, we’ll suppress the obvious “Hey Augie, this here looks like an FPGA to me!” and take a look at what Altera is bringing us. The leader in CPLD is introducing a formidable new competitor to the race. The new device family is a non-volatile, instant-on, 0.18µ flash, LUT-based architecture. The family ranges from 192 to 1700 “equivalent macrocells” meaning, as a CPLD, it’s about four times the density of previous Altera CPLD families, and significantly larger than even Lattice Semiconductor’s biggest offering. As a flash-based FPGA (OK, we said we wouldn’t, but…) it ranges from 240 to 2,210 logic elements, which puts it right up against the bottom of the Cyclone family.

Altera went back to Marketing 101 with the offering and asked “what do designers want and expect from a CPLD family?” Their answers came back with priorities such as lower dynamic power, higher density, more performance, non-volatility, in-system reprogrammability, lower cost, and a familiar design environment. When Altera set out to address these priorities, they settled on the LUT-based design.

MAX II offers about double the performance of the previous-generation MAX 7000AE family, and does so (according to Altera) at one-tenth the dynamic power consumption of their MAX 3000A family. This “best of both worlds” approach should serve to consolidate their offering as it gives designers of even battery-powered applications access to a lower-power, higher-performance, higher-density programmable option.

Another goody that comes along for the ride is embedded user-flash. By including flash on-chip, MAX II can be used in a variety of applications where a discreet EEPROM can be integrated into the CPLD, saving cost and board space.

What does all this mean? For Altera, it shows they have decided to “dance with the one that brought them” and to go back and do the serious engineering investment in CPLD that they’ve been letting slide for a few years. For CPLD-rival Lattice Semiconductor, it means a dangerous new competitor in the game that raises the ante with a new point on the price, density, performance, and power curve. It also means that Actel is still the only supplier of flash-based FPGAs (well, except for Altera’s new CPLD family).

It’ll be interesting to watch how this wolf in sheep’s clothing performs as it makes its way through the peaceful flock of CPLD offerings. I think I hear the quiet echoes of Andy Granatelli’s turbine-powered Indy car somewhere in the distance.

Kevin Morris, FPGA and Programmable Logic Journal

March 9, 2004

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