Stratix II - Altera unveils new 90nm architecture

Sides have been chosen. The gauntlet has been thrown down. The battle lines for the next generation of programmable logic have been drawn, and the games may now begin. Altera today announced its first 90nm FPGA architecture, and their strategy and offering contrasts sharply with that of arch-rival Xilinx. While it is far too early to call a winner in this contest, it is already crystal clear that the competition will be interesting, exciting and nothing but good news for FPGA designers.

Following the success of their highly regarded Stratix family, Altera today announced Stratix II. While movie-goers have long been trained that the sequel never lives up to the original, Stratix II represents a significant step forward from its namesake architecture.

New FPGA Fabric Architecture

Yes, Stratix II is built on 90nm technology, but that’s only the beginning. Belying the “II” moniker, this is a completely overhauled architecture that happens to also leverage the next process node. First and foremost on the list of changes is the radical (to those who follow FPGA architecture) departure from the traditional 4-input logic cell. 4-input look-up tables (LUTs) have been the stalwart atomic structure in FPGA for a number of years. Numerous analyses, experiments, and academic papers have shown that, on average, a 4-input structure is the most efficient fixed-size basic cell for generic implementation of most types of logic design.

Altera chose to break with that tried-and-true tradition; they have developed a novel variable-width cell called an “Adaptive Logic Module (ALM)”. An ALM looks something like a 7-input LUT (or 8 depending on how you count) that can be flexibly re-partitioned into a number of configurations such as 5 inputs + 3 inputs or 4 inputs + 4 inputs. With input sharing, larger combinations can be created, such as 5 + 5 or even 6 + 6. According to Altera, this architecture allows the best of both worlds – the efficiency of narrow logic elements with the performance of wide ones. With a 4-input LUT, for example, a 5-input function could require 2 levels of logic and up to 3 LUTs to implement. With the ALM, a 5-input function can be implemented in a single ALM with one level of logic and still leave room for an optional 3-input function (which might have required yet another 4-input LUT in the original case). This means substantially fewer gates are needed to implement the same logic, and often fewer levels of logic between registers. The net effect should be less area, higher performance, and fewer routing resources consumed.

Altera's new ALM architecture facilitates more efficient logic usage with repartitionable LUT structure.

In Altera’s suite of about 100 designs, this translates into an architectural improvement of 1.25X in logic utilization compared with the previous Stratix architecture. Normally, in this business, architectural changes produce results that are both mixed and discontinuous. Often an architecture “improvement” might significantly improve 70% of designs, have no effect on 10%, and seriously degrade the final 10%. In the case of the Stratix II ALM, however, the change seems to be almost universally positive. Over 95% of Altera’s test suite showed improved efficiency with the new architecture, a few with over 2X improvement and none with significant degradation.

Graph showing relative efficiency of ALM vs. 4-input LUT on Altera's customer design suite.

New Math, and more New Math

Changing the venerable LUT structure once again scrambles the way we (try to) count gates on FPGAs. Just when we thought we knew the multiplication factors for various vendors’ Logic Elements to LUTs to System Gates to ASIC-equivalent gates, along comes Altera’s ALM with a whole new math. Altera has tried to do the calculating for you, mapping Stratix LEs to Stratix II ALMs. As with any architecture that gets synthesized, packed, and mapped, your mileage may vary. The only accurate way to find out what device your design will require is to synthesize and map it with the tools you’ll be using, and then look at the final utilization reports. Otherwise, there are just far too many variables to make even a reasonable guess.

Also on the subject of math, in addition to the new ALM structure, Altera upped the ante in the DSP application area by significantly increasing the ratio of multipliers available for parallelizing datapath operations. This means that a much larger number of DSP processors could be subsumed into a single FPGA, with corresponding savings in cost, power, and board area. The largest member of the Stratix II family includes 384 18-bit multipliers - enough to do a lot of math in a hurry.

New Features

Equally significant for a number of application areas is the support for higher-bandwidth external memory. The continued acceleration of memory rates has driven FPGA vendors such as Altera to constantly upgrade their external memory interfaces in order to maintain at-speed compatibility with the fastest and most popular RAM available. There’s a significant increase in on-board RAM as well, with up to 9 megabits of on-board storage.

Next on the list of new features in Stratix II are 1Gbps differential source-synchronous signaling (try saying that one three times fast) with up to 152 receiver and up to 156 transmitter channels, combined with Dynamic Phase Alignment (DPA) circuitry, which simplifies the board design process with high-speed differential signals.

Rounding out the feature set is a new 128-bit encryption of design data based on the Advanced Encryption Standard (AES). This security feature should significantly reduce the threat of reverse-engineering and make the family more appealing to security-conscious development teams.

90nm Process

Stratix II is built on TSMC’s 90nm, all-copper process using low-k dielectric material on 300mm wafers. Altera actually moved to 300mm wafers at 130nm, so the gains here are strictly from the new process and geometry. One problem that is supposed to creep in at 90nm is power dissipation, but Altera claims to have held parity on power with the new architecture.

To you, 90nm means larger, faster, cheaper devices. The table below shows Stratix II sizes and specifications announced as of today:

What does it get you?

Altera claims that Stratix II offers 50 percent higher performance, double the logic density, and 40% lower cost than their highly successful Stratix family. What does that mean to the industry? First, Altera’s calculations show that Stratix II makes FPGA a viable option for even more designs that were previously on ASIC-only turf. Since performance and density limitations are often the show-stopper for programmable logic-based solutions, the increased capabilities of Stratix II could bring an estimated 17-18% more of the overall custom IC market into Altera’s crosshairs. Second, it means that existing FPGA applications can get a significant cost reduction and performance boost, particularly those taking advantage of the enhanced DSP capabilities.

The cost savings can multiply if, for example, Stratix II lets your application use both a smaller device (due to the revised architecture) and a lower speed-grade (due to the higher performance). If the additional multipliers allow the elimination of dedicated DSP processors, or a drop from two Stratix devices to one Stratix II device, the cost (and power) reductions could be even more significant.

Stratix II can handle Altera’s popular Nios soft-core RISC processor as well, and the combination makes a compelling solution for many applications. If volume production is in your future, consider that a HardCopy mask-programmable version of Stratix II is slated for 2005, so you could be ready by then to get more performance and even further cost-reduction by the time the bugs are worked out of your product.

Third-Party Tool Support

Both Mentor Graphics and Synplicity have synthesis support available. While the new architecture could have been challenging for third-party synthesis vendors, Altera absorbed most of the new architecture complexity into Quartus II. "Stratix II offers designers superior performance and flexibility,” says Simon Bloch, General Manager of Mentor Graphics Synthesis Division. “Its new Adaptive Logic Module (ALM) functionality allows a designer to optimize designs either for logic efficiency or performance, effectively offering the best of both worlds…Mentor has worked closely with Altera to ensure that Mentor's Precision Synthesis FPGA design environment takes full advantage of ALM functionality and other hardware architecture improvements."

Altera makes a practice of working with EDA vendors ahead of new architecture releases. The net result is that an (almost) full set of Altera and third party tools are ready to use now. The notable exceptions to this are third-party physical synthesis tools. These tools take longer to adapt to a new architecture, and they are more closely tied to the physical aspects of the device. It should take a few months for third-party physical synthesis support to be available. While Stratix II is higher-density than previous generations, it might well require proportionally less routing than previous generations, owing to the ALM architecture. Early experience with the Stratix II family will tell whether this will hold off the dragons of mandatory physical synthesis for a bit longer.

When can we use one?

Altera says it will begin shipping engineering samples in Q2, 2004. Stratix II is designed with Altera’s Quartus II version 4.0 (already released) and is already supported by third-party synthesis tools. There’s no reason you can’t start designing today.

Our Take

Our take is that Stratix II represents a significant step in FPGA technology advancement. We look for it to facilitate broader application of FPGAs across the board, but particularly in moderate-volume, high-complexity applications. For users of previous generation high-end FPGAs, it should offer significant cost reduction, higher performance, and greater gate density, raising the bar once again for crossover from FPGA to ASIC. For system-on-chip, and particularly for applications with high-demand DSP functions, it represents an even larger stride and could facilitate new applications that were previously technically or economically infeasible.

Additionally, the new fabric architecture is significant. As geometries shrink, power consumption, routability, and timing predictability all typically get worse. Altera’s ALM approach appears to help in all these areas, allowing the benefits of the new process node to come through without so many of the usual drawbacks.

Kevin Morris, FPGA and Programmable Logic Journal

February 2, 2004

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