Rose is a Rose - Platform FPGA vs. Structured ASIC

Your next design project requires some sort of custom IC. The device will aggregate several functions from your previous-generation product and needs to meet some modest power and performance improvement goals. Your company is going to produce probably a hundred thousand units of this design, maybe more if it is successful. The complexity and speed of the device would require a fairly expensive FPGA, pushing the unit cost to a point that would erode and possibly eliminate your profit margins. On the other hand, the cycle time, NRE, and risk of doing a cell-based ASIC are a stretch for your team and could be a showstopper for the project. You may be a customer for the new breed of semi-custom logic known as structured ASIC.

While FPGA costs have been dropping, the high-end devices have remained expensive, power-hungry, and somewhat performance- and density-limited compared with ASIC devices. New super-low-cost generations of FPGAs, while far more affordable than their high-end cousins, are deliberately limited in their capabilities in order to preserve the margin of the flagship devices. Applications that require the performance of high-end devices with volumes and price structures that demand the prices of the low-cost devices fall into a gap not well served by the current programmable-logic industry. At the same time, cell-based ASIC technology is skyrocketing away from this group as well, with increasing NRE, longer schedules, and higher risk factors.

These factors have combined to create a niche for a new kind of semi-custom mask-programmable device known as structured ASIC. Structured ASIC devices probably most closely resemble gate arrays as they are pre-manufactured and mask-customized by the addition of only a few metal layers. Where they differ from gate arrays is in the pre-fabricated cells. In addition to random logic fabric, structured ASIC devices come with a number of available larger-scale IP blocks pre-designed on the device. For the design team, this means less design, testing, and integration time, and lower NRE and mask costs. If the available IP is a good fit for your application (and here is the current Achilles’ heel), performance and power consumption can be comparable to a full-boat ASIC implementation. Compared with FPGA, a structured ASIC implementation offers potentially lower unit cost, higher performance, lower power consumption, and a smaller footprint.

Structured ASIC devices are somewhat new, and a handful of vendors are testing the market with initial offerings. NEC’s Instant Silicon Solution (ISSP) line already has a track record, with over 30 customers pushing designs into production. ISSP is actually NEC’s second foray into structured ASIC, and their recently announced 90nm version (ISSP2) is poised to be among the first structured ASIC platforms to hit that process node.

ISSP is based on a proprietary (probably somewhat FPGA-like) logic cell and is available in a range of sizes from just over 200K to 1.5 million gates with over 3.5 M bits of memory. They also offer gigabit serial I/O supporting a number of popular industry standards. Test structures are built into the device, simplifying the design process considerably. Clock and power distribution are also handled behind the scenes, making an ISSP device far simpler to design than a similarly complex cell-based ASIC.

ISSP’s metal-only customization can reduce NRE by a factor of five or more from cell-based ASIC methodologies. Design cycles are shorter as well. Performance is very close to cell-based ASIC with a significant power savings over FPGA. The more FPGA-like design flow also reduces the EDA tool requirements. NEC has partnered with Synplicity (the early leader in structured ASIC focused EDA) as well as traditional ASIC tool suppliers such as Synopsys. Synplicity has developed specialized tools for ISSP, including physical synthesis with its Amplify product, and the result should be shorter, more predictable schedules as the physical effects on timing are handled, preventing unconstrained design iteration.

ISSP2 promises to leverage 90nm technology, bringing higher densities and increased performance. Samples are due out this quarter with volume production later this year. In addition, a variety of IP is available and more is coming on line, making ISSP a true platform design solution.

LSI Logic offers its RapidChip technology in blocks called “slices” where each slice has application-domain-specific functionality built in. Slices include high-speed serial I/O, memory, ARM processors, and other commonly used functions. Like NEC, LSI offers lower NRE and faster time-to-market than cell-based ASIC with their offering.

Long time FPGA conversion player AMI Semiconductor has rolled out a structured ASIC line as well. Their XPA families have an architecture that facilitates easy conversion from Xilinx and Altera FPGA designs. Given AMI’s history in FPGA-to-ASIC conversion, the architecture makes great sense, as their sales channels already work with customers in this space. Their strategy apparently differs from LSI and NEC, who are poised to sell structured ASIC primarily to their traditional cell-based customers.

ChipExpress has specialized in the structured ASIC business with their CX2000, CX3000, CX4000 and now CX5000 lines, which represent 0.6, 0.35, 0.25, and 0.18 micron technologies respectively. The newly announced CX5000 line comes in several configurations, including the Memory Pig, which has up to 4.5M bits of RAM. As structured ASIC catches on, vendors will probably expand this type of specialized variation in capability, targeting more and more specific application domains.

Interestingly, many of the structured ASIC lines appear aimed at the recently lackluster communications and networking markets, where FPGA made its explosive growth a few years ago and still has a commanding presence. As communications companies struggle and consolidate, one obvious option is to replace legacy FPGA-based product offerings with cost-reduced versions based on mask-customized solutions.

FPGA vendors recognize the position of structured ASIC in the market and don’t want to leave a hole in their product line either. After an initial market test with their HardCopy Apex line, Altera has created a much more compelling solution with their new HardCopy Stratix technology. The key advantage of the FPGA-vendor-supplied solution is a continuous design flow from prototyping and early production with FPGA parts using Altera’s highly successful Stratix architecture to cost reduction and performance improvement using the HardCopy mask-programmed part.

Trading transistor-based routing connections for metal customization generates a smaller die, improved performance, lower power, and a smaller footprint, as well as eliminating the need for configuration logic. Otherwise, the IP used, the design tools and flow, and the debugging work done on the FPGA version all carry forward to the structured ASIC. As with other structured ASIC offerings, NRE and turnaround time are far less than that of a comparable cell-based ASIC part. In the case of HardCopy, the ability to use Stratix devices both as prototyping and as a sort of in-system emulator makes for an attractive package.

Xilinx challenges the Platform FPGA vs. Structured ASIC comparison with their new ASMBL architecture (see Per Holmberg’s article). ASMBL may be a harbinger of the new way of life in programmable logic, where generic devices gradually fade in favor of pre-configured parts that are tailored toward specific application areas. Xilinx recognized that many application areas have architectures that are 80-90% standard with only modest changes in the remaining logic to support new standards or differential functionality. By having pre-integrated parts with the major blocks for an application already in place, the job of creating a domain-specific application can be simplified and cost-reduced.

On the tool front, with the notable exception of Synplicity, EDA vendors are mostly playing wait-and-see on structured ASIC technology. Synplicity has made a major corporate commitment to structured ASIC by partnering with most vendors of structured ASIC devices and by creating vendor-specific versions of its synthesis and physical synthesis tools. If one reasons that the design tool usage and distribution model for structured ASIC will strongly resemble that of FPGA, Synplicity seems ideally positioned to capitalize on the emerging market.

Of course, many customers for structured ASIC are moving from the cell-based ASIC world, and Synopsys, as the dominant ASIC tool supplier, factors in heavily as well. As in FPGA, Synopsys leverages their huge ASIC installed base to providing broad-based tool solutions that span implementation technologies. Most structured ASIC vendors support both Synplicity and Synopsys synthesis flows.

Here, too, Magma appears well poised to join the game. With their acquisition of technology from Aplus Design Technology, they are positioning themselves as a supplier of structured ASIC physical synthesis technology as well.

The structured ASIC tool battle will be an interesting one. Because there are a large number of structured ASIC vendors, it is unlikely that silicon-vendor-supplied tools will capture much of the market as they did in FPGA. Without the silicon-revenue-based tools subsidy, it is also likely that tool prices will be higher than FPGA designers are accustomed to paying, albeit much less than corresponding cell-based ASIC tools.

On the demand side, with less NRE and schedule time at risk, design teams will not be as willing to invest stratospheric sums in verification tools, either. Combined with the simplified design flow, the tool budget for the design team should be substantially lower than in cell-based ASIC, while offering sufficient margin to entice EDA suppliers to invest in tool development.

The final tale of the tape on structured ASIC, however, will be customer acceptance of the silicon and IP offerings themselves. Structured ASIC will capture large market share only if the costs and schedules remain significantly smaller than cell-based ASICs while capabilities and volume unit costs remain better than FPGA. In any fast-paced technology market, filling a gap between competing technologies is a dangerous business, as technical advances on either side can squeeze the gap into irrelevance.

At a higher level, the structured ASIC movement emphasizes the validity of platform-based design. For years, RTL-based design and integration of an entire system has become increasingly unwieldy, and an effective higher-level language-based design methodology for general system design has never emerged. Aggregation of commonly used components into platform elements that allow design assembly in the same manner as traditional board design, however, appears to be the way of the present as well as the future.

Whether your target implementation is FPGA, platform FPGA, structured ASIC, or some variant of these, platform-based design is likely to be the methodology of choice. Look for vendors to create more and more competitive differentiation based on collections of IP and application-domain-specific devices tailored to specific markets. Also, watch for a greater number of players and an expanded range of options as new suppliers seek out market niches in emerging application areas where they can fill gaps in broad-line product portfolios.

Kevin Morris, FPGA and Programmable Logic Journal

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