Domain-Specific Platform FPGAs
by Per Holmberg, Senior Director, Virtex Marketing, Xilinx, Inc.

ASIC NRE costs and design times are skyrocketing. At 130nm, NRE can be $10M or more and the time needed to design an ASIC chip typically ranges from 12-18 months. In addition, application adaptability is often being included in the chip’s specifications. The need for adaptability is driven by several factors, including:

• A shift in the target market, often significant, during the year-plus design cycle for an ASIC
• Rapidly evolving standards, particularly for communications equipment
• Product differentiation, particularly for a range of products derived from a common platform
• Hardware reuse for succeeding product generations

Designers are turning to less costly alternatives than ASICs to reduce the time and financial resources they need to design a complex system-on-a-chip (SoC). Gartner Dataquest projects that ASIC sales will show an 8.4% compound annual growth rate between 2002 and 2007. More importantly, however, Bryan Lewis, Dataquest's chief analyst for ASIC, SoC, and FPGA research, notes that ASIC design starts will continue to decline, from more than 11,000 in 1997 to fewer than 4,000 in 2006. In contrast, a study from iSuppli forecasts much larger double-digit growth in the FPGA market—15.9% in 2003, 25.6% in 2004, and 26.4% in 2005. Further demonstrating the shift to FPGA designs, Hier Design’s Jackson Kreiter, in a September 1, 2003 EEdesign article, Why EDA shouldn't ignore FPGAs, notes, “In 2002, there were 90,000 FPGA design starts, which represents a more than 10-to-1 ratio over ASIC design starts.”

To help alleviate the pain of ASIC design, Xilinx has developed a new FPGA architecture, coined ASMBL, (Application Specific Modular Block Architecture). The new architecture will enable rapid cost-effective deployment of multiple domain-specific FPGA platforms with an optimal blend of features.

ASMBL Overview

ASMBL supports the concept of multiple, domain-specific platforms through the use of a unique column-based architecture (Figure 1). Each column represents a silicon sub-system with specific capabilities, such as logic, memory, I/Os, DSP, processing, hard IP, and mixed signal. Xilinx assembles the domain-specific FPGA by combining columns with different capabilities to target a particular class of applications (as opposed to application specific, which would address a single application). Typical domains might include logic-intensive, memory-intensive, or processing-intensive. For example, a processing-intensive chip for graphics processing might have more columns devoted to DSP functions than would a chip targeting an application in the logic domain.

Addressing Technical Issues

The ASMBL architecture offers benefits on two levels, addressing the issue of domain-based design along with addressing some of the technical limitations of both traditional ASICs and FPGAs. Specifically, ASMBL alleviates the problems associated with I/O and array dependency, power and ground distribution, and hard-IP scaling.

I/O and Array Dependency

Traditional chips fall into two general categories—core-limited and I/O limited. A core-limited chip is one where the size of the chip is dependent on the amount of logic it contains. The perimeter of the chip is more than sufficient to support the I/O, clock, power, and ground bonding pads surrounding the chip. A pad-limited chip has its size dictated by the bonding pads on its perimeter—the pads are as close as possible, consistent with the chip’s design rules, and there can be wasted, open area within the chip’s core.

ASMBL’s column-based architecture eliminates the area-periphery dependency problems associated with both core-limited and pad-limited designs. The left side of Figure 2 shows how a traditional pad-limited chip has to increase in size if the design needs to accommodate more I/O pads. The right side of Figure 2 shows how a chip using the ASMBL architecture can accommodate additional I/O pads without increasing in overall size by devoting more columns to I/O functions. Since cost goes up as die area increases, this can result in substantial cost savings. Similarly, if the design calls for an increase in functional (core) area, this can be done without adding more I/O blocks.

To support internally placed I/O blocks in a column-based architecture, ASMBL-based chips use flip-chip packaging, which allows bonding pads to be located anywhere on the chip, not just on the periphery. Flip-chip technology mounts the chip “upside down” in the package, with tiny solder balls connecting the various bonding pads (I/O, power, etc.) to the internal package interconnect. The solder-ball technique is then used to connect the package’s pins to a printed-circuit board or other substrate. Besides allowing internal pad placement on the chip, flip-chip packages also provide enhanced thermal dissipation over that exhibited by wire-bond packages.

Power and Ground Scaling

The ASMBL architecture also results in improved power and ground distribution on the FPGA. Similar to placing I/O pads internally on the FPGA, the designer can also distribute power and ground pads throughout the interior of the chip. Gary Smith, Dataquest’s chief EDA analyst, stated in an October 2002 Market Trends Report that, “Power has become the number one problem for design engineers...”

As process geometries shrink, supply voltages also scale down. Decreasing power-supply voltages along with increasing on-chip clock frequencies and data rates produce transient voltage spikes and ground bounce that make meeting a chip’s power and signal-integrity (SI) specifications very difficult. To overcome these problems, designers have to add additional power and ground pads to a chip to enhance power-grid distribution and reduce on-chip parasitic voltage drops. ASMBL’s support of internal power and ground pads simplifies the task of uniform power distribution across the FPGA device over what designers can do with a traditional chip having power and ground pads only on the chip’s periphery. This reduces power-supply droop, ground bounce, and clock skew (since clock buffers spread across the chip see a more constant VDD supply voltage and more uniform ground), reducing on-chip signal-integrity and signal-delay problems.

Hard-IP Scaling

A third advantage of ASMBL is the architecture’s support of hard silicon-IP scaling. For a rectilinear IP core in a traditional FPGA architecture, scaling the core upward to accommodate additional features might require a larger FPGA (Figure 3). Scaling IP in an ASMBL-based FPGA means adding more IP, implemented in columns, which can fit within the existing FPGA’s area. This, effectively, reduces the IP scaling problem from two dimensions (a rectilinear core) to one dimension (IP arranged in a column, with scaling accomplished by increasing the number of IP columns). Therefore, the designer does not have to go to a larger, more expensive chip to be able to scale the capability of the silicon-IP cores on the chip.

Column Architecture

ASMBL, with its column architecture, allows FPGA devices to be developed as domain-specific Platform FPGA devices, with even lower price points than not only prior generations of Platform FPGAs, but also Platform ASICs and Platform SoCs. By targeting an FPGA device for a domain rather than a specific application, the designer starts with a device that already has attributes tailored for a range of applications. The designer then can program the device to make it device-specific. The combination results in several levels of design flexibility for the chip.

This flexibility and the quick development time of the ASMBL architecture offers distinct cost and design-time advantages over platform mask-programmable chips—ASICs or SoCs—that contain pre-defined silicon IP and standard buses. Depending on required memory, logic, and I/O structures, either the top metal layers of a Platform ASIC or the entire chip are customized during fabrication to fit a specific application. If the application environment changes or the vendor desires a derivative device to handle a related application, the chip has to undergo a redesign to incorporate different IP cores and connectivity, along with a re-spin of some or all of the mask layers. This is expensive in terms of engineering time and mask cost.

By using ASMBL-based FPGAs to address a domain that encompasses a range of similar applications, designers can use one FPGA for multiple purposes. Changing applications is a relatively simple matter of reprogramming the device, thus making use of the inherent application adaptability of an FPGA. This offers the benefits of reduced time and risk in developing a Platform FPGA, a cost-effective development of multiple platforms addressing different applications, and a quick response to new market demands.

Per Holmberg, Senior Director, Virtex Marketing, Xilinx, Inc.

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