Does your child own an FPGA? Until fairly recently, the answer to that question would have been a confident “no,” but technology and market dynamics are conspiring to put programmable logic devices in places where we would least expect them. While the ASIC vs. FPGA debate has raged in the domain of low-volume, high-margin systems, things on the consumer product front have remained fairly quiet. There was no reasonable alternative to ASIC for very-high-volume projects such as toys and consumer electronics, due primarily to the enormous unit-cost penalty of programmable logic devices.

The good folks who brew up sophisticated FPGAs for us weren’t content with low-volume, high-production cost applications and prototyping. They saw huge market potential in bringing the joys of field-programmability into the realm of mass-produced systems. If a few nagging problems like unit cost, power, and performance could be solved, they reasoned, design teams could get products to market faster, handle engineering change orders more easily, and take advantage of flexible manufacturing inventory in ways that ASIC implementations could never match.

With ASIC design schedules often pushing a year or more and most FPGAs easily completed in 20 weeks or less, the market-share gains from being first to market with a new product generation can easily outweigh some incremental cost for an FPGA implementation. In fact, for many projects, the anticipated cost-reduction step of moving to ASIC never happens, as incremental feature requirements just roll the product onto another round of programmable-logic. Additionally, the vendors have been hard at work narrowing the incremental cost gap. The newest generations of devices from Altera, Xilinx, Actel, and Lattice specifically target low-cost/high-volume applications and differentiate themselves based on various aspects of performance in that realm.

Altera has a strategy of targeting specific end-markets based on volume, margin, and position in the technology adoption cycle. New technologies still in the concept stage may use traditional high-end FPGA devices for prototyping and proof-of concept. These projects typically have production runs in the tens to hundreds of units and are used to shake out the design and validate the functionality of the product before initial consumer adoption begins. In this space, high-end devices like Altera Stratix and Stratix GX, Xilinx Virtex-II and Virtex-II Pro rule the roost. These devices, while expensive, offer features that allow quick prototyping of products and boast features that have historically trickled down to lower-cost offerings by the time a new product might go to volume.

As new products reach the “emerging” stage of early consumer adoption, they shift priorities. Technologies (such as digital television today) that are beyond the prototyping stage but not yet in explosive volume growth need low enough cost to make high-end FPGAs infeasible, yet they still often need capabilities beyond what very-low-cost devices can offer. Altera recommends that designers of these systems employ a cost-reduction strategy with their HardCopy Stratix devices. HardCopy migrates the original high-end FPGA design to a 1-1 compatible ASIC-like mask-programmed technology. This cost-reduction strategy is used for high-complexity devices with production volumes in the tens of thousands. In addition to cost savings, these ASIC-migrations offer higher performance, lower power, and better security than their programmable cousins, all of which are important in high-volume applications.

Some vendors are thinking out of the box and offering innovative services that can drive down the unit cost in other ways. For example – if an FPGA device doesn’t test 100% good, it would usually be headed for the discard pile. It can’t be counted on to reliably implement some yet-unknown application with reliability. Most FPGA applications, however, use far less than 100% of the device. If the fault on an imperfect device isn’t in the part that your application uses, it might still work fine for your design (assuming you weren’t counting on field upgradeability or field-reprogrammability). If you’re doing high volume of a particular design, some vendors, such as Xilinx, with their EasyPath program, will allow you to send them your test program, and they’ll verify otherwise faulty chips to see if they work well for your particular application. For devices that pass, they will sell them to you at sometimes significantly reduced prices.

For even higher-volume fast-to-market applications in what Altera describes as the “aggressive growth” segment, designers turn to ultra-low-cost FPGA families such as Altera’s Cyclone and Xilinx’s Spartan device families. Products in this segment (including applications like set-top boxes and SOHO networks) are now out of the early-adopter realm and moving into the mainstream. The role of programmable logic in these applications is often reduced compared with earlier stages of the product life cycle. An ASIC or ASSP device may have taken over the bread-and-butter tasks, while an FPGA or CPLD handles advanced add-on features, interface tasks, and migration to changing standards. The driving design goal here is typically gate-count-per-cost, and current generation devices have made huge strides in this arena. “We are shipping million-gate cyclone parts today for $12 [US] in volume,” says Altera’s Todd Scott, director of the consumer business unit. The battle for low-cost supremacy is a serious one, and vendors are pulling out all the stops to get a share of the lucrative high-volume market.

Actel has recently upped the ante in this segment as well with new low-cost versions of their ProASIC Plus family. Part of Actel’s strategy is to differentiate their offering based on packaging advantages and total system cost, which can be key driving factors in this market. Because Actel’s devices are based on flash instead of the more common SRAM technology, they don’t require an external configuration memory or microcontroller. This can mean fewer total devices to mount on your board, and with their newly announced small-footprint packages and increased I/O density, they’re looking to capture a piece of this rapidly growing market.

So, what’s the difference between these very capable low-cost devices and their high-end cousins? In the past, it was a process generation. The biggest, fastest, high-margin devices were fabricated on the latest technology, and their low-cost cousins were based on the previous process. Now that may be reversing and the current families of high-end devices are differentiated by advanced features like gigabit I/O, memory, and embedded processors. This is a line the FPGA suppliers have to walk carefully because they don’t want to cannibalize their established high-margin markets by making a low-cost device too capable. At the same time, they don’t want to lose out on the high-volume business by offering a less capable low-cost device than their competitors. Watch for a variety of strategies from vendors in differentiating low-cost offerings from both competitive products and from their own high-end silicon.

Still today, in the “maturing market” segment with accepted consumer technologies like DVD players, there is little or no FPGA content. These applications have already been through one or two phases of cost reduction, and the only programmable logic left will typically be CPLDs doing glue-logic or interface tasks. In this space, suppliers like Lattice Semiconductor jump into the fray with industry leaders Altera and Xilinx. A large portion of Lattice’s business comes from supplying very high volume CPLD parts for high volume systems such as consumer products. By focusing on key concerns of the consumer market such as power dissipation and packaging while maintaining just enough performance and capability to serve the market needs, they’ve carved out a business that’s somewhat less volatile than the leading-edge of FPGA.

So, besides cost-per-capability, what are the key considerations in deploying programmable logic in high-volume and consumer applications? “As FPGAs have grown in size and complexity, the need for secure logic devices has become apparent. More often than not, the key intellectual property is housed in programmable logic, and as a result, the vulnerability of each system’s unique value-added characteristics is now a direct function of an FPGA’s security capabilities,” says Actel’s Barry Marsh, Vice President of Product Marketing. Because of the inherent reduced security of SRAM-type devices that have to be programmed with a companion memory, Actel has seen interest in their flash- and anti-fuse-based devices from companies interested in protecting their intellectual property. Lattice has attacked the security issue as well by combining configuration elements onto the device itself. In some markets, the reverse-engineering starts the minute a products ships in volume, and manufacturers want to keep their competitive advantage as long as possible.

Another emerging concern is environmental friendliness. According to Altera, their Cyclone devices are among the first accepted by Sony’s Green Partner program for environmentally friendly devices, and Lattice has recently had their entire line certified. More and more high-volume producers are interested in reducing the content of environmentally sensitive materials, particularly lead in the case of semiconductors, as large quantities of discarded consumer equipment finds its way into landfills.

While one doesn’t normally associate programmable logic with battery-powered applications, vendors are working hard to reduce power consumption to make portable applications a reality. Lattice semiconductor’s new ispMACH 4000z Zero-Power CPLDs target high-volume and low power applications and are available in temperature ranges suitable for more demanding applications such as automotive and industrial systems. This is one area where focused suppliers like Actel and Lattice are challenging the leaders by specializing in areas where mainstream SRAM-based FPGAs aren’t well suited and there is considerable product volume to support a healthy market.

Where is low-cost programmable logic going next? It’s going to be getting smaller. Quite a bit smaller, in fact, as 90nm devices start to roll into full-volume production. Unless you’ve been hiding under a rock, you probably have been reading about the semiconductor fabs tooling up for the 90nm process node, but what does that mean for you as a consumer of programmable logic?

First, it means that your child may well end up owning an FPGA - potentially a lot of them. Between the smaller geometry and the concurrent increase to 300mm wafers (that’s about the size of an old LP record album!) cost-per-gate of semiconductors in general is going to go through the floor. According to Xilinx, the combination of 300mm wafers with 90nm technology offers a 5X advantage over the current flagship technologies (which are 200mm wafers with 130nm). The 300mm wafer offers a 2.35X increase in area, while the 90nm allows a 2.09X increase in density. This translates into much lower silicon costs, as well as reduced power consumption and higher performance – all attractive to the typical high-volume designer.

Xilinx was the first to jump on the 90nm bandwagon as they announced their new Spartan-3 series this month based on 90nm process technology. Don’t look for the full cost/volume benefits quite yet, though. Current speculation is that the true benefits of 90nm won’t hit the volume price lists until late 2004 when yields increase. The Xilinx announcement claims full volume production will begin in early 2004 with early-announced prices taking effect later in that year. Teams starting the design process now, however, may be ready to order in volume at the right time to take advantage of the real cost benefits of the new technology.

Xilinx also announced that the new low-cost Spartan-3 family will be their first on the new process. This represents a shift from previous generations, where the high-end Virtex families lead the charge onto a new process node. The reasons for this strategy shift can be found in the change in market and design dynamics. Today, there is increasing pressure to drive costs down in order to expand programmable logic to new (and higher volume) markets. At the same time, the design cycle time for the high-end devices has climbed drastically due to increased complexity. Since there is more demand on the low-cost end, and high-end designs take longer to design, it makes sense to have the cheap, fast-to-market silicon available first with the more exotic parts becoming available in time for the longer design projects to complete.

During the last five years or so, another interesting shift has hit the semiconductor industry. Where programmable logic used to be late in the adoption of a new process node, today’s FPGAs are an attractive architecture to shake out a new fabrication technology. The fairly regular structure of FPGAs combined with very high volumes and markups has put them at the front of the line for implementation in a new technology. As a result, FPGAs now typically enjoy about a one-process advantage over other types of parts. This can help to offset the inherent inefficiencies of programmability.

As these initial offerings from programmable logic vendors meet with some success, look for more and more variety and capability in device offerings as the vendors go after specific markets with targeted, almost ASSP-like devices. Don’t be surprised to see an increase in both the diversity of programmable logic and the number of viable suppliers. As the criteria for success broaden from speed, gate count, and price to include power dissipation, footprint, packaging, support-circuitry, security, IP availability, reliability, and environmental friendliness, the opportunities for niche suppliers will only improve. The net result will be faster, more flexible new product development cycles, with more and more opportunities for ASIC displacement by programmable logic. An FPGA-based 300MHz, data-driven, wi-fi enabled teddy bear may be on your kid’s toy shelf sooner than you think.

Kevin Morris, FPGA and Programmable Logic Journal

October 21, 2003

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