Mr. Moore's Wild Ride - 90nm FPGAs go mainstream

Designing with FPGAs offers you protection. It offers protection from the risk of ASIC re-spins and NRE, protection from design rule worries, protection from test generation, protection from high-cost design tools… The FPGA vendor did all the work, took all the risks, and made all the mistakes for you, so you could design in peace and harmony, unthreatened by the demons and dragons of IC design and process technology. From the “safe” side of that protective wall, however, it’s sometimes difficult to discern whether the barrier is getting gradually thinner.

As each process generation has brought its new challenges, programmable logic vendors have responded with new, innovative architectures, more capable tools, and improved methodologies. The recent announcement by both Altera and Xilinx of 90nm-based devices rings the opening bell on the next round of this game. 90nm is clearly the most challenging geometry jump of the decade, and FPGA vendors continue to struggle to bring to designers the benefits of the technology while preserving the wall of safety that makes FPGA the world’s most popular technology for implementation of customized logic.

The 90nm challenge is a multi-dimensional contest. FPGA vendors are seeking to expand their technologies to broader markets, diversifying their way to safety from the vagaries of the volatile communications market whose roller-coaster ride rocketed them to prominence in the late 1990s only to plummet them into the grips of the recession of the early new millennium. They are also working to differentiate their product offerings and add value as the pending expiration of patent portfolios threatens to homogenize and commoditize the market. Crossing these strategic agendas are the technical challenges of the process geometry itself: increased power dissipation due to leakage current, greater noise susceptibility, compatibility of the lower-voltage process with legacy technologies, and the usual yield challenge in bringing up a new generation. At the same time, most fabs are also midway through the transition from 200mm to 300mm wafers.

At the nexus of this melee are the marketing machines of the vendors themselves, each working to position their company as technology leader and supplier of choice for a new wave of inductees into the programmable logic club. It is here that the drama unfolds. Xilinx made the early push into 90nm, fueled at the time by UMC’s apparent lead over TSMC in the new process. Having experienced a greater-than-anticipated struggle with their 130nm lines, they were emboldened to jump ahead into the 90nm market.

In a sharp departure from convention, expectation, and the rest of the pack, Xilinx decided to bring their low-cost Spartan line to production first rather than their high-end Virtex line. Analysis of the factors involved reveals this to be a well-conceived, bold, and strategic move. First, the challenge of yield could be partially overcome by the relatively smaller die size of the low-cost line. Second, the square millimeters shaved off of each die translated into square watts of heat that didn’t have to be dissipated in fighting the power glut induced by the step increase in leakage current at the 90nm node. Third, in the effort to diversify out of the high-cost telecommunications market into more cost-sensitive application areas, a highly competitive low-price product would be a strategic advantage, particularly to counter the highly successful price/performance point of arch-rival Altera’s successful Cyclone line.

Meanwhile, Altera was embarking on their own 90nm adventure by redesigning their flagship Stratix architecture to produce Stratix II. This was a longer and more perilous road than the low-cost path, resulting in about a 10-month differential in announcement dates. Altera had already put enormous effort into consumer-level cost reduction with Cyclone, however, and saw a successor to Stratix as the best way to continue their comeback in the high-margin, high-performance segment. Altera combated power and complexity issues by replacing the traditional 4-input LUT architecture with a new partitionable, variable-input logic cell called an ALM. This combination of architectural changes and process geometry bump give Stratix II impressive benefits over previous generation technologies.

Probably the most successful dissenting voice continues to be that of Actel. Actel has succeeded in differentiating their offering from their larger competitors by leveraging alternative (non-SRAM-based) technologies. The benefits of those alternatives (which we’ll discuss in an upcoming article) include smaller footprints, instant startup, lower power, improved environmental immunity, and greater security. None of these differentiators gains significantly from a move to 90nm. Actel argues that 90nm requires a significant engineering trade-off to be made between power, speed, and cost, and every vendor moving to the smaller geometry will have to optimize for one of these variables at the expense of the others.

Indeed, both Xilinx’s and Altera’s offerings reflect quiet compromise in this space, and the difficulties faced by the semiconductor industry in general in getting to 90nm speaks to the challenge of juggling these factors in a commercially successful way. A number of manufacturers, including AMD, Fujitsu, IBM, Intel, LSI Logic, NEC, TI, and Toshiba, all predicted shipping 90nm in 2003. Here in 2004, however, it is possible that only the Xilinx/UMC partnership is shipping 90nm silicon in volume.

Sony’s claim to be in volume production at 90nm with their EE+GS@90nm device has now been disputed and is the subject of ongoing debate regarding exactly what constitutes 90nm. With annotated images from a scanning electron microscope, Canadian-based Semiconductor Insights released a claim this week that the Sony device, while at advertised dimensions, may in fact be based on 130nm design rules.

Photo courtesy Semiconductor Insights.

Bypassing this controversy, both Xilinx and Altera have now officially launched their offerings, and their diversity works to your advantage. In the ensuing scrimmage of superlatives, conflicting claims have been made on all sides with words like “largest”, “fastest”, and “cheapest” being batted around with subtle subtext qualifiers such as “production”, “available” and “shipping today”. While the marketing wits struggle to win the war of perception, there are practical technical realities that merit some mention.

First, unlike previous process jumps, it is likely that your first 90nm FPGA designs will consume more, rather than less, power when compared to similar 130nm designs. With the narrower gate and lower supply voltage, leakage current (even when not switching) becomes significant. The smaller voltage swing also increases susceptibility to noise and crosstalk. Process improvements such as low-K dielectric, silicon-on-insulator (SOI), and multi-gate transistor designs have proved to only partially control the problem. The complete solution to power problems may be the first place where 90nm pierces the protective wall of the FPGA option.

Power reduction techniques such as gated clocks and low-power micro-architectures are design-specific and require designer involvement. They can’t just be built into the FPGA fabric itself. More pressure will therefore be pushed upstream to the development of EDA technologies such as architectural and RTL synthesis and physically-aware logic design to automate the application of these techniques. Until such technology matures, however, the burden of low-power design to make effective use of 90nm technology may fall through to you, the end-user.

The higher density afforded by 90nm will also exacerbate timing problems caused by unpredictable routing delays and (not at all to the dismay of the EDA industry) accelerate the need for physical synthesis technology in achieving timing closure on complex designs. As we’ll discuss in an upcoming article, EDA companies such as Hier Design, Magma, Mentor, and Synplicity are working to keep pace with more powerful physical design tools of their own. If you’re planning high-complexity 90nm designs, one of these tools may be in your future if you want to keep development schedules under control. The remainder of 90nm bounty, however, such as lower cost, higher performance, and greater density, should be available to you without significant hurdles to overcome.

Despite many naysayers’ predictions, Xilinx is shipping Spartan 3 in volume and taking record orders as a result. Xilinx expects the combination of 90nm technology and 300mm wafers to give almost a 5X advantage in full production with a 2.35X increase in die-per-wafer from the 300mm wafers, and another 2.1X density increase from the 90nm geometry shrink. Initially, Xilinx ramped production by going to market with 90nm devices fabricated on 200mm wafers. This allowed them to take one step at a time, working out the bugs on the new technology with the older, smaller wafers, and then making the cost-reduction jump to 300mm, gaining additional production capacity along the way.

Xilinx delivers world's first 90nm, 300mm FPGA. (PRNewsFoto)

Xilinx reportedly has 5X more design registrations for Spartan 3 devices than any other Xilinx family, with over 200,000 of the devices scheduled for shipment in Q1 2004. The Spartan 3 design registrations also represent over 40% of all Spartan series registrations, indicating a strong early customer migration to the new family. Xilinx is also seeing strong adoption of Spartan 3 in their newer target markets such as PDPs, LCDs, and HDTVs, fueling their diversification and market-expansion strategy. Two members of the Spartan 3 family are now shipping in production, with 6 of 8 now sampling. The full family is scheduled for production by mid-2004.

Altera’s 90nm Stratix II (described in last week’s feature article) is coming to market with similar fanfare. Based on TSMC’s 90nm process, Stratix II is one of Altera’s most ambitious projects to date. In addition to 90nm and the new fabric architecture, Altera has added generous helpings of multipliers and memory to make the offering even more attractive to high-growth areas such as DSP-on-FPGA.

Altera chose to offer their higher-performance, higher-margin, lower-volume devices first on 90nm while yields are difficult, rather than attempting Xilinx’s counter-intuitive strategy of trying to get high-volume, low-cost parts out of a new process. Altera reckons that their new line achieves 50 percent higher performance, double the logic density, and 40% lower cost than their already capable Stratix family. These factors combine to make the devices a compelling solution for a significantly larger segment of the mid-range ASIC pie, and the eventual addition of a HardCopy-structured ASIC conversion option with associated cost reduction will cut into the ASIC lean even more deeply.

With the two major vendors hopping onto 90nm in two completely different market segments, the clear winner is the customer. Now, a leading edge 90nm part is available in both price/performance areas, and a mainstream 130nm offering is available from both vendors to back it up. Whatever you’re designing today, you can design for the 90nm solution with reasonable confidence. Even if you have some difficulties along the way, there is a proven 130nm fallback solution from each vendor, and any issues you have with the 90nm version are likely to be resolved before your project goes to any volume.

Although it’s too early to tell for sure, reason would suggest that 90nm will also place an increased demand on design tools. Increased complexity of designs will require simulation, synthesis, and place-and-route tools with greater capacity than previous generation technologies. With an increased proportion of delay from wiring likely, the errors in timing analysis due to unpredictable routing delay will increase, making physically-aware timing optimization tools more of a necessity, and increasing the likelihood of unpredictable numbers of iterations from RTL through synthesis and place-and-route. Finally, pushing the speed and capacity of these devices to the limit is more likely to produce issues with power dissipation and may require more capable tools for power analysis and design techniques for reducing power dissipation.

What you won’t see in 90nm is what the vendors faced in bringing you these devices. Designing an FPGA requires extensive analysis of the target architecture using an enormous variety of design types. There simply is no good way to predict the things that designers will attempt once a device is in the field, so the factory has to try as many possibilities as they can and guardband to cover the majority of the cases. With past process generations, the main concerns were routability, yield, timing, and clock and power distribution on the device.

With 90nm, the problem was more difficult because of the specter of leakage-current-related power problems. Since overall power consumption is dependent not only on the target design, but also on the stimulus that will eventually be applied to that circuit, the problem of testing a representative number of configurations grows exponentially. Additional issues such as crosstalk and noise immunity are more of a concern at 90nm as well, and design software as well as hardware architecture became part of the solution. Beyond this, the sheer size and complexity of these devices put new levels of stress on the design tools used by the vendors themselves such as design rule verification and test. If 90nm seemed slow in coming, remember it’s no small achievement that it got here at all, and it is a testament to the skill of the FPGA vendors’ engineering teams that they beat most of the industry in the transition.

Does 90nm take away some of your margin of safety in choosing the FPGA option? The answer is probably “yes”, but the benefits in terms of potential cost savings, higher density, and greater performance will be worth the extra effort and risk for many applications. The early move of FPGA to 90nm also bodes well for programmable logic in general. As broader markets and higher volumes stabilize the suppliers and the supply, they also fund the opportunity for increased R&D and ultimately better cost/performance ratios where we all will reap the rewards.

Kevin Morris, FPGA and Programmable Logic Journal

February 10, 2004

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