For years, programmable logic has been the Cinderella of the ASIC family – left to clean up the scraps while the “real” ASICs got the glory and did all the important work. This best-supporting-actor role flowed into many design teams too, where the less experienced engineers were relegated to FPGA duty, while the superstars got to work on the ASIC.

As ASIC costs skyrocketed, however, many companies started to look at the feasibility of using FPGAs for more than just consolidating the leftover logic from the project that couldn’t, for some reason, go on the ASIC. While the FPGA solution would solve many of the most difficult problems with ASICs: frequent revisions, long lead times, huge NRE charges, and moving standards, FPGAs had their own limitations that prevented them from being useful in key roles in many, perhaps most, applications. Aside from the well-known cost, gate-count and operational-frequency limitations, FPGAs were power-hungry, lacked the rich libraries of IP available on ASICs, had little or no memory flexibility, and couldn’t get data on and off the chip at the required speeds.

Today’s high-end FPGAs (and, as we discussed in our “Pinching Pennies” article, even many new very-low-cost ones) have addressed these issues and are finding their way into a central role in more and more systems. FPGA manufacturers have delivered this capability, thanks in part to three quietly revolutionary innovations: high-speed smart I/O, flexible memory architectures, and hard/soft IP libraries.

While Moore’s law has predictably pushed FPGAs along the same track as the rest of the semiconductor market, other changes have been brewing with accelerating effects on programmable logic. Even with increasing speed and gate count, as long as data was stuck waiting at the boundaries of the FPGA, there was little reason to invest in elaborate on-chip system designs with programmable logic. That changed when astute vendors began adding rich high-speed serial I/O capability to their devices.

In the communications domain, programmable logic was the reasonable choice for converting from massive parallel backplane busses to faster, more flexible and reliable gigabit serial I/O. While much of the application was already handled with ASSPs or ASICs, the rapidly changing nature of serial I/O standards as well as the inherent flexibility and scalability requirements created an opportunity for a specialized class of devices aimed at handling just the SERDES and related portions of the design.

Lattice semiconductor, with its acquisition of technology from Agere Systems, was well positioned to stake a claim in this rapidly emerging market. According to Jock Tomlinson, VP of FAEs and Strategic Accounts, Lattice has a broad portfolio of gigabit serial I/O devices targeting backplane communications and now rack-to-rack communications. “Compared with parallel standards, SERDES provides higher performance and noise immunity, simplified backplane design, and fewer points of failure,” says Tomlinson. The serial approach also allows for easy scalability, as throughput can be increased by simply adding additional channels.

Although most use of gigabit serial I/O is in off-board communications, the idea is beginning to catch on for chip-to-chip communication as well. As packages with over 1000 pins become commonplace, the additional overhead of serial I/O is sometimes justified by the need to improve reliability, decrease pin requirements, and simplify board design. Both Altera and Xilinx have many of the popular and emerging standards supported on their high-end and even some on their ultra-low-cost general-purpose devices such as Altera’s Cyclone and Xilinx’s Spartan families.

Today, the race for serial supremacy is one of the most furious in programmable logic, as high-speed differential serial communication replaces parallel busses in the mainstay communications segment and branches out to more general applications as the cost drops and the design techniques become more widespread.

All this ability to get data onto the device, process it, and get it off again drove a voracious appetite for memory on FPGAs. While external RAM has always been the norm, some classes of applications demanded access to flexible-architecture on-chip memory to meet spec. Here again, the vendors went back to the lab to try to overcome the inherent inconvenience of merging a configurable memory architecture into an FPGA fabric. During the memory battles that ensued, vendors tried various combinations of single- and multi-port block and distributed memory modules of varying sizes, speeds, and dimensions. While many of these efforts proved less than optimal for many applications, a couple of generations with a lot of experience working with end-users produced architectures that are very effective, especially for the mainstay communications market.

Today, most high-end FPGA architectures have a small-medium-large approach with individual cells or LUTs acting as registers, cascaded groups of elements acting as reconfigurable single- or multi- port RAM for mid-size needs, and large dedicated RAM blocks for more demanding uses.

The inclusion of these flexible on-chip memory elements allows for high-speed designs such as DSP to queue and store data locally without the cost of off-chip access. In addition, they provide application memory for many of the emerging embedded applications using the new wave of hard- and soft- IP based processors.

In the land of ASIC, there has long been a robust IP industry selling a variety of useful, proven functional blocks that could be dropped onto your device with minimal design effort on your part. In programmable logic, however, this rich library of IP didn’t exist. Eager to resolve the situation, programmable logic vendors created large internal groups developing libraries of IP targeting their architectures. While this was a short-term fix for the problem, in the longer run it stunted the development of third-party IP for FPGA because the vendor-supplied IP was heavily subsidized by silicon revenues, and commercial IP suppliers were reluctant to invest in developing IP for a market where prices were already set low.

In the past two years, the market dynamics have changed somewhat. First, the prices of high-end FPGAs raced into the thousands of dollars. This made the price of commercial IP fairly insignificant by comparison. Second, with the advent of embedded systems on FPGAs, the need for IP increased significantly. Designers wanting to take advantage of the time-to-market advantages of platform-based FPGAs needed ready access to complex peripheral IP. Third, the complexity of the design process increased almost geometrically from the previous generation of devices. A more sophisticated design team was required to successfully complete a design, and proven IP was a fast way to combat rising design costs and expanding schedules. Finally, the capability of FPGAs improved to the point that some very non-trivial functions could be implemented in FPGA without severe headaches meeting timing specifications.

In addition, the vendors picked some very-generic capabilities that were performance-sensitive and began offering tailored devices with ASIC-like hand-optimized implementations of some functions such as microprocessors and DSP-enabled arithmetic operators. This dropped the performance penalty for FPGA compared to ASIC for those functions. These hard-macros, however, created the demand for even more soft-IP to support the capabilities they provided.

As a result, today there are an increasing number of commercial IP vendors certifying their cores for use in high-end FPGAs. The available IP includes processor and DSP cores, bus-based peripherals, and a host of vertical-market-targeted standard functions designed to facilitate almost drag-and-drop system creation for some classes of end-market applications.

Many customers were burned early, however, and quickly learned to be sure the IP they planned to use was qualified for the particular technology they were targeting. Using IP that was originally designed for ASIC and not qualified for programmable logic can have disastrous outcomes. The reasons for this lie in the difference between ASIC and FPGA strengths. In ASIC, registers are expensive, and logic is cheap, so designs are often created with micro-architectures that call for long chains of logic between registers. In FPGA, however, registers are often virtually free and long chains of logic can cause timing catastrophes when layout effects are factored in. Performance-sensitive IP such as PCI cores, particularly those architected for ASIC use, can require significant floorplanning and hand-massaging to operate at spec on an FPGA.

Yankin Tanurhan, Senior Director of Applications and IP Solutions at Actel says that Actel took the approach of carefully qualifying third-party IP for use with their devices. “We realized we can’t supply everything for every application,” says Tanurhan. “We formed strategic partnerships with companies that provided qualified, verified blocks targeted at specific application domains.” Such an approach allows programmable logic vendors to supply solutions that meet the demands of various segments such as DSP, networking, or microcontrollers without having to become specialized in every target application area.

The cores with the most general applicability, however, are typically still supplied by the vendors themselves. Actel’s recently announced 8051 core follows on the success of Altera’s NIOS and Xilinx’s Microblaze 32-bit processors providing embedded systems frameworks for a variety of end-applications. The ability to use a standard processor and re-use the associated software elements in a variety of designs across a wide range of devices is proving much more popular than trying to match up a device with a hard-core processor that has a particular embedded application.

Taken together, these three additions to the programmable logic palette, although created primarily with telecom customers in mind, have ushered in a completely new era of diverse applications of FPGAs. The possibilities created by the combination of high-speed I/O, rich IP libraries, and embedded memory to support them has only begun to be tapped by the systems design community. As the true capability of these innovations used in combination becomes apparent, there will be more and more applications opened to programmable logic. There is also likely to be more and more diversity in features such as these, as vendors differentiate their product offerings and produce devices that are increasingly useful for a wider variety of applications.

Kevin Morris, FPGA and Programmable Logic Journal

[back to top]

Comments on this article? Send them to comments@fpgajournal.com