A Sleeping Giant Awakes
Synopsys enters FPGA - for real

Synopsys is no stranger to the FPGA market. They have made several fateful forays onto the playing field of programmable logic in the past. Like Salvador Dali’s “Gala Contemplating the Mediterranean Sea Which at Twenty Meters Becomes the Portrait of Abraham Lincoln,” the true nature of Synopsys’ FPGA strategy was best observed from a distance. From up-close, it appeared that they were putting meager development effort into a mediocre product that was nearly given away in the EDA industry’s closest thing to a commodity tools market. From far away, however, maybe even with your eyes blurred a bit, another explanation emerged. It is possible that the company, whose lifeblood was a 9-digit annual income from ASIC synthesis, was entering the FPGA market as a defensive strategy. By offering adequate tools for a pittance, they helped discourage the fledgling FPGA synthesis suppliers from gaining the monetary momentum that would allow an upstart competitor to develop synthesis technology that could compete with their flagship Design Compiler.

That was then, and this is now. The new reality has three important differences from the days when Synopsys last actively played in FPGA. First is the fact that the high-end ASIC synthesis market is now driven by risk aversion rather than technology leadership. Most design team managers who value their jobs are not going to gamble an NRE on any tool other than the one that has proven itself on thousands of ASIC designs, regardless of the possible features, benefits, and productivity gains offered by a competitive tool. Second, although Synopsys’ strategy may have postponed the inevitable, a competitor, Synplicity, has managed to develop synthesis technology that rivals theirs. Third, with design starts migrating to FPGA from every direction – ASIC, DSP, SoC, and ASSP, it is impossible to maintain a belief that an ASIC-centric market will continue to account for the majority of EDA revenue. In the same painful way that the FPGA market had to come to grips with the necessary diversification beyond telecom, the EDA market must now accept that building more and more expensive and complex tools for a smaller and smaller ASIC design community is not the path to growth.

Synopsys this week announced their new FPGA synthesis product line, and it is apparent from both the offering and the strategy that they are well aware of the changing winds. This is not chapter 4 of the story that began with FPGA Express, FPGA Compiler, and FPGA Compiler II. This time, there is no obvious hole in the strategy – no lackluster product priced to be ignored by its own sales force, hoping that no Obleo steps forward to point out that the emperor has no clothes.

Synopsys has clearly analyzed the new reality and has crafted an immaculate plan that capitalizes on the depth and breadth of their corporate capabilities and market position to capture a lucrative share of the growing FPGA tools market. Synopsys’ proposition is simple: if you’re prototyping ASIC designs using FPGAs, this is the tool to buy. Their sales force doesn’t have to go out and meet new prospects. They’re already there. They don’t have to convince customers to shell out bigger-than-usual bucks for FPGA tools with elaborate analysis of ROI from advanced features. The people who need this tool will gladly pay the price. In the best “would you like fries with that” tradition, Design Compiler FPGA will be added to the orders of hundreds of design teams stocking up on technology tools for their next system design. These are not the “Fred in the Shed” designers that make up as much as three-quarters of the FPGA-designing population while accounting for less than 10% of the silicon revenue (according to our 2003 FPGA Project Survey). These are well-funded teams in systems companies who take advantage of the breadth of custom silicon technology all the way from high-end ASIC to CPLD as well as the full-range of EDA tools regardless of cost, and who are looking for any advantage that gets profitable products to market quickly and reliably.

While the FPGA vendors’ paychecks are signed by high-volume production designs, EDA makes its money from design starts, not silicon sales. Approximately half of all FPGA design starts are for prototyping purposes, so Synopsys has wisely put their emphasis on capturing that market. The beauty in this strategy is that Synopsys is uniquely positioned to offer an end-to-end solution to these design teams. No competitor can make a more credible claim to providing a product line that allows seamless transition from FPGA to ASIC with minimal migration headaches. Synopsys’ plan is quite simply to run uncontested by focusing on a huge, lucrative, under-appreciated segment of the FPGA market. Because the prototypers might (justifiably) be seen as second-class citizens in the eyes of the FPGA companies (by purchasing single-digit quantities of devices), they have been under-served by those companies’ tool strategies. ASIC design teams who prototype with FPGA are already Synopsys’ bread and butter, however, and by offering them seamless FPGA/ASIC solutions now, they not only reap the incremental revenue of the new product sales, they also position themselves for future success by seeding the major design teams with their FPGA synthesis technology. If those teams (doing FPGA prototypes for ASICs today) decide in the future to migrate to production programmable logic, they already have the tools they need. Synopsys doesn’t need to make a separate product pitch to capitalize on the market shift.

The FPGA vendors may not be getting rich selling silicon to prototypers, but they are soundly on-board with Synopsys’ strategy. Tim Southgate, Altera VP of Software Tools, says “ASIC designers are increasingly adopting FPGAs for prototyping as part of their verification flow. With the introduction of Altera’s high density Stratix II family, over 50 percent of ASIC design starts can now be prototyped on a single FPGA. While historically this required two separate design flows, the availability of DC FPGA now allows ASIC designers to use a single design environment.”

Rich Sevcik, Executive Vice President of the FPGA Products Group, Xilinx, says “Synopsys’ new Design Compiler FPGA combined with industry leading FPGA technologies from Xilinx can deliver a significant cost savings and time-to-market advantage to our customers. With DC FPGA’s excellent timing performance and unified FPGA and ASIC design flow, Synopsys users can now realize the full potential of the Xilinx high-performance Virtex-II Pro and Spartan-3 devices.”

The technology lynchpin, and potential Achilles’ heel, of this strategy is synthesis quality of results (QoR). If Synopsys can deliver synthesis results that are on-par with FPGA technology leaders such as Synplicity, they can count on the rest of their advantages to deal them a winning hand. If a competitor can demonstrate superior answers, however, particularly in the area of timing closure, Synopsys will be vulnerable to attack. While previous Synopsys offerings have fallen short in QoR, initial indicators are that things may be different this time. Synopsys’ press release claims “best timing with 15% improvement over existing FPGA solutions.” It also bears noting that this is the first FPGA Synthesis product to which Synopsys has seen fit to attach their franchise “Design Compiler” moniker.

While EDA vendors’ QoR claims are historically dubious at best, there is reason to give these claims some credence. First, Synopsys arguably has more synthesis experience and expertise than any EDA company in the world. If they want to develop a leading-edge solution, they certainly have the resources to do so. Second are the initial reactions from customers and FPGA vendors. While it might be tempting to dismiss these as typical product release partner rah-rah, the FPGA vendors are historically cautious about commenting on EDA vendors’ results, partly because they don’t want to diminish the perceived capabilities of their own bundled solutions, and partly because they are in a position where they actually know the answer. Most FPGA vendors run exhaustive QoR measurements on every available synthesis tool targeting their technology and evaluate the capabilities of those tools based on their results. Through agreements with the EDA vendors, they unfortunately refrain from publishing what they know, but one can get at least a blurred picture of the answer through their public comments, and these comments seem to indicate that Synopsys has done well with their new product.

Ironically, this pivotal announcement takes place the same week as the controversy heats up over the irrelevant archeological announcement by Dataquest of two-years-ago “results” in the FPGA synthesis market. If those suspicious statistics had no bearing on reality before, they are now completely relegated to the realm of novelty. We predict that the next two years’ FPGA synthesis market will bear no resemblance to the previous five, and the Synopsys announcement this week is only the beginning.

Kevin Morris, FPGA and Programmable Logic Journal

March 16, 2004

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