Somewhere, in another building perhaps, is another engineer just like you. He spends every day working on the same project as you. He went to engineering school just like you did. He even hooks up his logic analyzer one probe at a time just like you. You probably don’t go to the same cocktail parties, however, and chances are you don’t sit together at company picnics. In fact, he may be thinking bad thoughts about you right now. Why? Because while Moore’s law may work just fine for you, it generally makes his life more difficult, and your new 1500-pin FPGA may be the scourge of his professional life these days. He’s the guy designing the board that your new super-duper Stratix GX or Virtex-II Pro will park on, and you need to find out what his problem is before it’s too late.

In the good-old days when “deep-submicron” meant 0.8µ, and “high pin-count” meant a 256PGA, the board designer didn’t have to worry too much about FPGAs. Even though almost every printed circuit board contained at least one programmable logic device (and still does), the FPGA never caused too much heartburn. Now that we talk about nanometers instead of microns, and we have pin numbers with four digits, however, the picture has changed. We need to examine the effects of modern FPGA packaging and performance on printed circuit board design and look at ways to mitigate the problems.

First, let’s look at the administrative issues. The board schematic is typically maintained by a different team than the one designing high-end ASIC and FPGA. In ASIC design, the pin-out is usually nailed down early in the design process and doesn’t change much as the project progresses. In the case of FPGA, however, the pin-out is constantly changing. Moving I/O assignments around on the device is an easy way to solve many timing problems, and FPGA design teams regularly take advantage of this flexibility. Down in board-land this is not well received.

In addition, ASIC gave the board team the luxury of long lead times. Since it took months of verification, analysis, mask-making, prototyping and double-checking before the ASIC was ready for the board, there was no big rush to get the PCB design finished. ASIC design was the long pole in the tent. Now that the centerpiece of the board is an FPGA however, the board team is more and more often finding themselves on the critical path. FPGAs typically require less than half the design time of ASICs and can easily have working silicon ready for on-board testing in a quarter of the time. This leaves the board design team less time than ever before to handle an increasingly complicated problem.

Cadence recommends tackling the challenge even before the board schematic is captured. “In today’s board design environment, building constraints into the design process is one of the biggest issues”, says Brad Griffin, Product Marketing Director at Cadence. “The Cadence PCB design environment is optimized for high-speed design and includes the industry’s first fully-integrated constraint management system and a robust common database that ensures data integrity throughout the design process.” According to Cadence, as high-speed design rules are created and subsequently refined, they must be imprinted into the design database to drive the PCB design process. Much like the FPGA design environment, the board flow is comprised of a suite of tools that pass design data back and forth. Also like FPGA, the designer’s constraints drive the design process. Having a standardized way to capture those constraints and a well understood semantic interpretation of them can considerably smooth the connection between designer and design environment.

Every time the pin-out changes on the FPGA, a new board schematic symbol has to be created, and it has to be correct. On a 200-pin device, that task could be handled in a couple of hours by the boss’s son who’s interning for the summer. On a 1500-pin device, however, it can take a real engineer a week or more to get the symbol modified and confirm that it’s right. If you’re changing your pin assignments every week or two during your design process, you’re probably not making any friends in your board group.

So common are these problems that Mentor Graphics has decided to include solutions to them by default in their flagship Board Station and Expedition products. Mentor’s FPGA Board Link automates the process of migrating pin-out changes between the FPGA vendors’ layout tools and their board-schematic environments. “In the 1500-pin range, creating symbols for FPGAs is quite a formidable task,” says John Isaac, Mentor’s director of system market development. “In addition, some symbols won’t even fit on a schematic sheet, so we provide user-directed fracturing of symbols across multiple sheets.”

While pin-count has been growing, much of that growth has been accomplished by increased interconnect density. These tight pin grids require boards that can’t be routed with normal laminate processes and require high-density interconnect (HDI) technology, including microvias and other advanced fabrication techniques, to fan-out the connections to the point where they can be routed normally on the board. In combination with embedded passives and other board-level technology upgrades, the sophistication of both manufacturing processes and design tools and techniques is being forced upward.

High pin count FPGAs in ball grid arrays (BGAs) often require layers
of HDI with microvias to fan out the signals onto the PCB.
(diagram courtesy of Mentor Graphics)

It might appear that the latest generation of FPGAs, with their high-speed serial I/O capabilities, might make the board designers’ lives easier by replacing massive source-synchronous parallel busses with differential-pair serial I/O. Originally designed for reducing bus widths and improving speed and reliability in communications backplane connections, these technologies are increasingly being applied to chip-to-chip communication on a single board. Unfortunately, this doesn’t seem to be translating into lower pin-counts or increased available board real estate. As more pins become available by switching from parallel to serial I/O, system designers are using them by adding more serial pairs to increase bandwidth or to add additional functionality to the FPGA.

Down in the board team, this means that the old tools and techniques for analyzing board-level timing have to be seriously reworked and augmented. The operating frequency of these new differential serial signals requires a completely different analysis approach and considerably more sophisticated tools. In addition, while the smart I/O configurations available on sophisticated FPGAs makes the FPGA designer’s life simple with near plug-and-play compatibility, the party can turn sour in a hurry if timing and signal integrity problems creep in at the board level. Serial I/Os can be programmed for different levels of pre-emphasis based on driven routing loads on the board, but there currently are no easy back-annotation paths to get this information from the board analysis tools into the FPGA design domain. This means that more communication is required between the FPGA and board design teams, which in an era of increased outsourcing, can be difficult.

High-frequency traces in very close proximity to one another increase the probability of cross-talk and other failure mechanisms. The primary solutions to these problems include simulating large streams of data in eye-diagrams to isolate and correct problems.

FPGAs utilizing Third Generation I/O (3GIO) multi-gigabit per second serial
interconnect now require eye-diagram analysis to ensure signal integrity on the PCB.
(diagram courtesy of Mentor Graphics)

For differential signal routing, this means that each differential pair needs to be tuned so that the routing for each phase of the differential pair has the same length and is phase-matched for the desired frequencies. The design of these paths must go even into the domain of the FPGA vendor, because the traces inside the packaging can make a significant contribution to performance issues when the package is designed onto a board.

These challenges have not gone unnoticed by the programmable logic vendors who have previously been blissfully isolated from serious board design issues. Now that more and more designers are facing board-related challenges, an increasing amount of FPGA vendor applications engineering time is being consumed resolving board-related issues. Lattice Semiconductor, who has put an emphasis on high-speed serial I/O technology, has developed detailed application notes for designing successful systems with their devices utilizing current mode logic (CML) and low-voltage differential signaling (LVDS) interfaces. Similar application notes have been developed by most vendors and should be a first stop for design teams tackling high-speed serial design for the first time. Reading the app-notes in advance can prevent headaches at the end of your project and may save you from having to send your favorite vendor AE a holiday turkey for bailing you out at the last minute.

These challenges are actually good news for the folks who make EDA tools for board designers. While the board design tool market has fallen into somewhat of a commodity space over the past few years, the added challenges of new high-density high-performance boards required for today’s FPGA-based designs means a new generation of design tools is required. This gives EDA vendors an opportunity to upgrade and differentiate their product offerings and to get a premium for new, leading-edge analysis tools required for these advanced boards.

Mentor Graphics offers a broad suite of design tools addressing high-end board design challenges. While their Expedition and Board Station products provide schematic through layout design and implementation capabilities, HyperLynx provides signal integrity and EMI analysis functionality, Tau provides board level timing analysis, and their ICX solution offers sophisticated simulation and analysis capabilities for both high-speed design and verification.

Cadence’s board tool suite includes ConceptHDL for design entry, SPECCTRAQuest high-speed design environment integrating the constraint-driven design and analysis process with design-in kits, Allegro PCB layout system, and SPECCTRA high-speed auto-router. As new gigabit I/O standards have proven difficult for even the savviest designers, Cadence has begun to work with vendors to produce design-in kits that help to contain the complexity of designing compatible board/package systems utilizing these standards. As a first step in the FPGA arena, Cadence and Xilinx have partnered to produce a design-in kit for Xilinx RocketIO.

Every EDA company we interviewed is actively investing development resources in this re-born board tools area, so watch for a stream of introductions, innovations, and improvements in the months ahead. This boost comes not a moment too soon as design teams struggle to cope with the exploding complexity brought about by today’s high-end devices. Next time you get a break, walk down the hall or over to the next building. Meet the folks that design the boards. The key to any solution for board-FPGA integration issues is communication and common methodology between design teams, and that can start with you.

Kevin Morris, FPGA and Programmable Logic Journal

November 11, 2003

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