Aurora Lightweight Gigabit Serial Protocol
by Abhijit Athavale, Marketing Manager, Connectivity Solutions, Xilinx, Inc.

The System Interconnect Challenge

As CPU speeds approach the multi-gigahertz range, system designers increasingly focus on system interconnect as the primary bottleneck at all levels, viz: chip-to-chip, board-to-board, backplane, and box-to-box. Most of the system interconnect used today uses parallel I/O technology with either source-synchronous clocking or system-synchronous clocking. The venerable PCI bus is the prime example of a system-synchronous interface that has served the industry well over the past decade. PCI uses a central arbiter that allows sharing of a common bus between several clients. This has obvious limitations since the bus bandwidth is not infinite – this in turn limits the capabilities of the clients. Additionally, this technology does not scale well when translated to backplane or box-to-box interconnects. Source-synchronous technologies using LVDS I/O were the next obvious choice for designers as they are point-to-point interconnects that do not have a central arbitration scheme bottleneck. However, these schemes suffer from the same problem that PCI based schemes did when scaling the technology across backplanes or box-to-box interconnects. Not only do designers have to run tens or even hundreds of traces in some cases over many inches of FR4, they also have to be mindful of the lane-to-lane data and the clock-to-data skew. A bit arriving too early or too late can cause serious link integrity problems.

The Serial I/O Advantage
The most logical evolution of the system interconnect now leads us to multi-gigabit serial I/O with clock-data recovery (CDR). This technology not only reduces the number of traces running across boards, it completely eliminates clock-to-data skew while reducing lane-to-lane skew effects for traces running tens of inches. Elastic buffers (FIFOs) available in multi-gigabit transceivers (MGTs) provide high skew tolerance for channel bonded lanes, up to 7 ns typical. The channel bonded lanes aggregate individual lane bandwidth to provide more channel bandwidth.. For example, a 10G backplane link that would need approximately 64 LVDS I/O running at 622 Mbps, would only take 16 pins or 4 MGTs running at 3.125 Gbps. This allows the designer to cut system design costs by reducing the board area and number of PCB layers as the number of pins being used is dramatically reduced. Another significant advantage of this technology is the flexibility afforded to the designer when scaling this system. The designer can easily partition his system since there is no need to run too many signals on backplanes or boards. Plus, the total link power is also reduced. For example, a 10G SPI-4.2 link would consume approximately 4W while a similar 10G XAUI link would consume about 2.8W. See figure 1.

Figure 1.

System Interconnect Standards

To take advantage of the benefits offered by serial I/O technologies, a number of standards have been introduced including PCI Express, RapidIO serial, Gigabit Ethernet, 10G Ethernet XAUI, and Fibre Channel, in addition to SONET at various data rates. All of these standards can be mixed and matched depending upon the user’s application – whether it is in the control plane, the data plane or the backplane – and come with their own set of challenges such as:

• Serial interfaces require special initialization and monitoring
• Very high bandwidth has to be managed inside the chip
• Channel bonding and flow control are complex tasks
• Maintaining the correct balance between high level features and total chip area required by the solution

The Aurora Protocol from Xilinx is designed to take advantage of the benefits of serial I/O while addressing its challenges. Aurora is a scalable, lightweight, link-layer protocol that can be used to move data across point-to-point serial lanes at a baud rate limited only by the MGT capability, for example, the Virtex-II Pro X device can transfer data in excess of 10Gbps per lane. Aurora is an open protocol and can be implemented in any silicon device/technology including FPGAs, ASICs and ASSPs - a fully functional Bus Functional Model (BFM) is provided to enable ASSP and ASIC integration.

Aurora can encapsulate packets from upper layers of proprietary or industry standard protocols such as Ethernet or TCP/IP. This allows designers to upgrade their hardware while making no changes to the software or firmware – which translates into big cost savings.

While primarily targeted at chip-to-chip and board-to-board applications, Aurora can be used for box-to-box applications with the addition of standard optical interface components.

Aurora Technology Overview

The Aurora Protocol describes the transfer of user data across an Aurora channel. An Aurora channel consists of one or more Aurora lanes. Each Aurora lane is a full-duplex serial data connection. The devices that communicate across the channel are called channel partners (figure 2).

Figure 2.

The Aurora interfaces transfer data and control to and from user applications by way of a user interface. The Xilinx reference designs use a standard packet passing interface, called LocalLink, to implement the user interface. Data flow consists of the transfer of user protocol data units (user PDUs) and user flow control messages between the user application and the Aurora interface, and the transfer of channel PDUs, and flow control PDUs across the Aurora channel. User PDUs can be of any length and is defined by the specification.

The Aurora Protocol Specification defines the following:

• Physical layer interface: This includes the electrical levels, the clock encoding, and symbol coding.
• Initialization and error handling: This defines the steps required to prepare channel partners for communication across single lane and multi-lane channels. It also describes how the channel partners should behave in the presence of bit errors in the channel.
• Data striping: This describes how data is mapped across a channel of multiple serial lanes.
• Link layer: This describes how the beginning and end of user PDUs are marked during transmission. This also describes how data pauses may be inserted in data during transmission and how differences in clock rates between the transmitter and receiver are managed.
• Flow control: Aurora defines a link layer flow control mechanism and an expedited mechanism for forwarding higher layer user flow control messages.

Figure 3.

LocalLink User Interface

LocalLink is a high performance, synchronous, Xilinx standard point-to-point interface, designed to serve as user interface to system interconnect solutions. The interface defines a set of protocol transparent signals that allow for the transfer of generic packets. Figure 3 shows an example of the LocalLink source interface functioning as the receive interface of the Aurora design, with the destination interface being the user’s application logic. A typical interconnect solution will have separate interfaces for receive (source) and transmit (destination) paths. The LocalLink interface features:

• Interface for packet oriented data of arbitrary length
• Synchronous point-to-point communication
• Upstream and downstream flow control
• Efficient channel bandwidth utilization

Aurora Deliverables

All Aurora deliverables are available free of charge from the Xilinx website at http://www.xilinx.com/aurora upon acceptance of a license agreement. The deliverables include the Aurora Protocol Specification v1.2, the Xilinx LocalLink Interface Specification, the Aurora reference design v2, and supporting demonstration designs for standard Xilinx development boards. The Aurora bus functional model (BFM) that supports Aurora Protocol v1.2 is also available free of charge. It includes advanced features for precision testing and characterization of any Aurora implementation. The Aurora BFM supports all the popular simulators on Windows, Sun Solaris, and the Linux operating systems including ModelSim, VerilogXL, VCS, NCVerilog. Fully parameterizable reference designs for FPGA based implementations are also available at the website.

Abhijit Athavale, Marketing Manager, Connectivity Solutions, Xilinx, Inc.

February 17, 2004

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