FPGA-PCB Co-Design – More Than Just Data Transfer
by Rob Irwin, Manager, Brand Strategy, Altium

The issues associated with integrating the design of large-scale FPGA devices and the PCBs they sit on have been brought into the spotlight with recent tool announcements from EDA companies Altium Limited and Mentor Graphics. This article looks at the issues and examines the tool support needed to make FPGA-PCB co-design a reality.

It’s been hard to miss the mounting flurry of industry reports touting the potential & broad use of programmable devices lately. More than any other single factor, the emergence of low-cost, high-capacity FPGAs is having a huge impact on the business of designing electronic products. Already it is claimed that more than 60% of board design turns include at least one CPLD or FPGA, and this figure is escalating.

Just as the advent of the microprocessor had a profound impact on electronics design, a new wave of change is being brought about by the FPGA ‘arms race’. And just as processor-based design required radical changes to design flows, the successful integration of large-scale FPGAs will require engineers to think differently about the design process. Similarly, EDA tool vendors must rise to the challenge and deliver automation and integration across traditionally disparate phases of the design process.

The changing role of FPGAs

Programmable logic is not only claiming an increasing amount of PCB real estate, but the role that programmable design is playing within both product development and the end-products themselves is also changing. While programmable devices have traditionally been relegated to support functions, such as providing configurable glue logic for on-board controllers or processors, the range of applications for these devices is increasing rapidly. Engineers are fast discovering the programmability (and potential re-configurability) benefits these devices provide, both during the design process and even after delivery of the product.

As the price/density threshold continues to drop, FPGAs provide an obvious alternative systems-development platform without the astronomical NRE and tooling costs imposed by ASIC design flows, making them an increasingly compelling option for consumer applications. What’s more, the capacities of the new generations of FPGAs coming onto the market provide vast development platforms that engineers can use to migrate more system functionality from the PCB into the programmable environment of the FPGA. In fact it is now possible to implement a complete system – processor, memory, communications and networking peripherals and glue logic – into an FPGA costing under US$20 in quantity.

Using FPGAs as a system platform has some compelling benefits, not the least of which is rapid chip development cycles. But time saved in the development of the FPGA circuitry does not automatically translate to faster time to market for the end product. When you deal with devices that can have upward of 1000 pins, most of which are user-configurable, there are significant problems associated with incorporating them onto a PCB and connecting to off-chip devices. This can negate much of the time saved in the FPGA development stage.

Propagating data between the FPGA and PCB

Typical FPGA-PCB design flows today comprise an ‘over the wall’ approach to propagating design data. In general the FPGA designer will lock certain signals to specific pins during the development of programmable logic. The remainder of the pins are assigned by the FPGA place and route tools. The pin mapping is then thrown over the wall to the PCB designers who use this to create their board schematics.

Of course, little or no consideration is given to board routing issues during the initial pin definition. The result is that the board designer is left with a sub-optimal solution that can potentially lead to the need to add more PCB layers, increasing both PCB design time and the cost of the final board.

Because the transfer of pin information between FPGA and PCB design tools is currently mostly a manual process, there is limited scope for the board designers to make major changes to the FPGA pin map. The pain associated with transferring these changes back to the FPGA tools often overrides the gains.

The reverse is also true. Once pins have been assigned in the FPGA, the designer will be loathe to change them because of the disruption and potential for errors it causes on the PCB side. If changes are made to the internal circuitry of the FPGA, the designer will often constrain the place and route tools in order to minimize changes needed to the pin map. Once again the result can be sub-optimal.

The result is that current projects involving large pin-count FPGAs tend to be more sequential than necessary. The FPGA design progressed to a high level of completion in order to tie down pin assignments before transferring the data to the board design stage. The focus then tends to be on minimizing changes to the pin map to avoid the errors and time associated with propagating these changes.

Synchronization is the key

To begin to overcome the difficulties involved in managing the integration of large-scale FPGAs onto a PCB, the process of data propagation must be automated. This requires a high degree of integration between the FPGA development tools and the PCB design tools, with the aim of allowing I/O changes to be freely flowed between the two design realms. In effect the design tools must enforce synchronization between the top-level FPGA I/O definition, the board-level schematics and the PCB layout. Given the historical gulf between FPGA design tools and board-level design tools, this is not a trivial process.

The first step in this integration is to create a link between the output of the FPGA place and route process and the board-level schematic representation of the programmed FPGA that is used to define the PCB design connectivity. This link enables the transfer of all relevant pin information to the board-level schematics. The board design tool then uses this information to drive both the PCB layout and routing process, as well as feeding into board-level signal integrity analysis of the board with the integrated FPGA using the pin models supplied by the FPGA vendors.

The next step is to make this data flow bi-directional by providing the ability for the board designer to automatically flow pin changes back into the FPGA design. This bi-directional data exchange is critical to achieving any level of concurrency in the FPGA and board design processes.

Historically, FPGA design tools have been supplied by the FPGA vendors themselves in order to propagate the use of their devices. These tools have dominated the FPGA landscape, but because the FPGA vendors lack experience and technology in the PCB design area, they provide little or no integration with board design solutions.

Recently, two of the major EDA companies, Altium Limited and Mentor Graphics, have used their experience in and technology in both FPGA and board-level design to release design solutions aimed at bridging the gulf between the FPGA and PCB.

Mentor’s I/O Designer is a stand-alone I/O management system that sits between the company’s FPGA and PCB design products. Altium has taken a slightly different approach with its Protel 2004 board-level design system. This system provides a single integrated environment for both PCB and FPGA design that allows both the FPGA and PCB design teams to work natively with the underlying design data from both areas of the design.

Figure 1 - Altium's Protel 2004 provides an integrated PCB and FPGA development environment that allows full synchronization between FPGA and PCB projects

Both Altium’s and Mentor’s products allow bi-directional synchronization of pin information between FPGA and PCB projects, giving both the FPGA and PCB design teams the ability to make pin changes throughout the design process without the overhead of manually propagating the design updates.

This significantly enhances the engineers’ ability to iterate between PCB routing constraints and FPGA place and route to achieve an optimal solution on both sides of the fence.

Automation on board

While pin synchronization is a key element in successfully bringing large-scale FPGA-based designs into the physical PCB realm, true co-design requires an increased level of automation within the board design process itself. Closer collaboration between the FPGA and PCB design teams early in the project can avoid some PCB integration issues, but the reality is that the initial pin mapping that comes out of the FPGA place and route process is usually nowhere near the best solution for meeting board constraints.

Pin synchronization allows changes to made within the PCB project and automatically flowed back to the FPGA, but the process of actually optimizing the design for board routing to conform to the necessary physical constraints can be very time consuming to do manually, even if the pin I/O and bank configuration is available to the PCB designer. The need for manual optimization limits the number of design iterations that can be performed and still meet project schedules, and thus leads to a conservative approach to pin swapping at the PCB end.

One unique feature of Altium’s Protel 2004 system is the ability to be able to automate the process of optimizing the pin assignments based on the physical characteristics of the target FPGA device and the net-level connectivity on the PCB. Pin swap constraints can be set up from the device’s bank information and the defined I/O types. Once mapping of the allowable pin swaps is done, the net-level pin assignments of the FPGA are automatically optimized to minimize crossovers and net length based on the PCB constraints. Critical nets can then be locked down at the PCB end and the new pin constraints passed back to the FPGA place and route tools, which automatically optimize the design to meet the FPGA timing constraints.

Figure 2 - The effect of running Protel 2004's automatic FPGA pin optimization - net length is balanced against crossovers to achieve optimum pinout for routing

Because optimization is automatic at both ends of the process, iterations can be done as needed to converge on an optimal solution that meets both FPGA and PCB design constraints. This eliminates the need to tie down non-critical I/O data early in the design process and allows the FPGA design and the board-level design to be carried out in parallel. Minimal time is lost when changes need to be made in the FPGA or on the board.

The only constant is change

The old adage that the change is the only constant is never truer than with FPGAs. Automating the board-level FPGA pin optimization is crucial if the full benefits of the reconfigurability of the FPGA platform are to be exploited by the mainstream of electronics designers. As more system functions are moved inside an FPGA, the placement and routability of the FPGA becomes the major factor determining the final cost of the production PCB. It is therefore essential that board design tools support the ability to easily optimize the integration of these devices and the inherent high pin counts that they entail.

For example, it is crucial to the successful layout of a board that large components are optimally placed. A slight rearrangement of the position or orientation of the major components can make the difference between being able to route the board with a given number of layers, or having to increase layer count and therefore increase cost.

PCB designers can take advantage of the fluid nature of the I/O assignments on an FPGA by trying different placement options and optimizing the pinout at each stage to determine the effect on routability.

Similar to this is the selection of device packaging. Currently, not only the device family, but the device package needs to be selected early in the design process in order to start the board-level design process. With the automation of pin optimization on the PCB comes the possibility of changing the FPGA device packaging selection later in the project. For instance, the project may initially specify a high-pin count BGA device during development, but once the actual I/O needs are tied down the packaging can be changed to a QFP type device to simplify the board manufacture. The new package can be specified in the PCB design and the pinout re-optimized to accommodate it.

‘FPGA-readiness’ key for mainstream board design

The inherent advantages offered by high-capacity, low-cost FPGA platforms in terms of flexibility and shortening of design cycles makes them impossible to ignore and a perfect medium for mainstream electronics design. The ubiquitous Moore’s Law will see an escalation in capacity and capability of these devices, while at the same time lowering unit costs even further. The extensive penetration of FPGAs into broad ranging electronic market segments, including traditional ASIC strongholds, is inevitable.

The key to unlocking the potential of this vast new market is the ability to provide mainstream system engineers with tools that are ‘FPGA-ready’. This is particularly important for board-level designers, as they will increasingly need to come to terms with the integration of FPGA devices with their board designs. It is clear that EDA vendors who fail to provide tight integration between FPGA design and board-level design will seriously disadvantage their customers as programmable devices inevitably find their way into many of tomorrow’s products.

The minimum requirement is bi-directional data transfer between the FPGA and PCB design projects. Beyond this, board-level design tools must be ‘FPGA-ready’ and support automatic optimization of the FPGA pin configuration for board routability to allow fast iterations through the circuit implementation process.

The good news for designers is that the spotlight has been turned on and is focused on the issues associated with effective FPGA-PCB co-design. The major EDA tool vendors are releasing real products that address these important areas. Using these tools, innovative companies can start to gain the significant benefits that programmable devices offer, and build smarter, more feature-rich products while reducing the costs and time taken to design them.

by Rob Irwin, Manager, Brand Strategy, Altium

August 24, 2004

About the author: Rob Irwin has a Bachelor of Engineering (Electrical) from the University of Sydney, Australia. He has over 20 years experience in the electronic design industry and currently holds the position of Manager, Brand Strategy at Altium Limited.

© Copyright 2004 Altium Limited. All rights reserved.

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