Packing Processing Power
Altera Introduces Nios II

Attention please! The days when embedded soft-core processors on FPGAs were novel little micro-controllers you could use instead of a hard-wired state machine are now officially over. Thank you.

You could use Altera’s new Nios II processor as a convenient replacement for a hard-wired state machine in your next FPGA design. You could also play Pong on your Pentium 4. In both cases, you’d be missing the point and seriously under-utilizing your processor technology.

This week, Altera announced the long-anticipated sequel to their popular Nios soft-core processor, and it is quite impressive. In short: speed, flexibility and capability – up; size and cost – down. If you’re a hardware designer, you may puzzle at the soft-core concept. Wouldn’t hard-wired processors work better in the same way that hard-wired multipliers do? If you think that, bookmark this page, walk across the hall, and have a discussion with an embedded software developer. (They’re really quite approachable and some of them even keep candy on their desks.)

In case you couldn’t locate a software engineer, here’s a brief rundown. First, you use a processor only when you want it, and the FPGA vendor doesn’t have to make the device more expensive by including hard-core processors that many customers will not need. Second, you need to use only enough resources to make the particular processor you need for your application. The new Nios-II family ranges from an “economy” version that consumes a miserly 500 logic elements (less than 20% of a low-cost Cyclone device) to a “fast” version (rated at over 200DMIPS on a Stratix II FPGA) that requires just over a thousand. Third, you can configure the processor to have just the special features you need without paying for what you don’t need. With configurable caches, custom instructions, and varying pipeline depths, you can create a processor that is perfectly suited to your application. Finally, it may not be a question of which processor to use, but how many. With a 220DMIPS (fast) Nios II CPU requiring only 1% of a large Stratix II device, you can pile them on your FPGA like parmesan on pizza.

It would be easy to evaluate Nios II in a vacuum, but failing to look at the bigger picture would sell short the potential of this powerful processing environment. In the larger context of FPGA-based reconfigurable computing, you can use parallel processing, custom instructions and hardware acceleration to push the performance of this platform into the stratosphere. For some applications, the combination of parallel Nios IIs running algorithms and control with hardware acceleration of math-intensive datapath processes (leveraging the built-in hardware multiply/accumulate resources of Stratix II) could drive your DMIPS off the map.

If you’re worried about the bus bandwidth required to stitch together all those processing elements, you can rest easy. Altera has included the Avalon switch fabric interconnect which bypasses bus contention in most applications and gives a higher-performance pipe between processors and peripherals.

Nios II comes in three basic sizes (compared with two flavors of the original Nios): “Fast” with the highest processing performance, “Standard” with a balance between price and performance, and “Economy” with the lowest logic utilization (and therefore lowest effective cost). The middle-of-the-road “Standard” Nios II is 10% smaller than the small Nios core and over 2X faster than the fast Nios. If you feel the need for speed, the “Fast” Nios II is 4X faster than the fastest Nios, while consuming about a third fewer logic elements. When squeezing onto a cost-conscious Cyclone, the “Economy” version weighs in at only half the size of the smallest Nios. Using the cost-optimized Cyclone series, this means a Nios II can be dropped into your design for as little as 35 cents worth of logic.

The Nios II family includes a library of IP with peripherals, memory interfaces, bridges, hardware accelerators, and custom instructions. Headlining the new peripheral lineup are a JTAG UART providing a single JTAG connection (for device configuration, code download, debug, target STDIO, and flash programming) and a compact flash interface for mass storage. Including partner-supplied IP, there are over 60 Nios II compatible cores available already. The Avalon switch fabric interconnect is automatically generated, and the kit includes an “import wizard” that can be used to bring in and connect custom logic to your processor environment.

The Nios II itself is licensed royalty-free on a perpetual basis, so you won’t be piling up royalty charges if your Nios II-based product is successful. It also simplifies the business model and reduces the overhead for dealing with complex licensing schemes.

Architecturally, the Nios II is a 32-bit pipelined RISC machine with full 32-bit datapath, 32 general purpose registers, 3 instruction formats, and “on chip” hardware multiply, shift, and rotate. Nios II also has separate instruction and data caches that are configurable for performance/area tradeoffs. All versions of Nios II can accommodate up to 256 custom instructions, allowing a wealth of acceleration options.

Much of the original Nios family’s success was due to Altera’s approachable and capable development tool suite. Altera realizes that as their embedded processing environment becomes more powerful and sophisticated, the focus of their development tool offering needs to expand to become friendly to software engineers as well as hardware engineers. This is a difficult task, as the two disciplines overlap considerably in the embedded systems space with each group using a slightly different vocabulary and thinking about the problem from a different perspective.

Altera’s new Nios II Integrated Development Environment (IDE) is based on the increasingly popular “Eclipse” base, and includes advanced hardware debug features, flash programming support, and a software-friendly interface that will feel at home to software engineering types. The Nios II development kit also includes the Micrium MicroC/OS-II RTOS and a lightweight IP application to support TCP/IP. In addition, Nios II is supported by a variety of other RTOS options including ATI/Mentor’s Nucleus Plus, µCLinux, KROS, NORTi, and prKERNEL v4. Supported Debugger environments include Altera’s own Nios II IDE, ATI/Mentor’s code lab, Sophia Systems’s Watchpoint, and First Silicon Solutions (FS2)’s ISA-Nios/T.

Altera bills Nios II as “The World's Most Versatile Embedded Processor ,” and the wide range of configurability options combined with the giant step forward in price/performance may prove them right. As the embedded processor battle heats up, we should see FPGA-based systems capture a larger and larger segment of the embedded computing market, and, as the design community begins to understand, explore and exploit the true potential of this reconfigurable computing capability, we should see technology innovations such as Nios II translate into some truly exciting end-products.

Kevin Morris, FPGA and Programmable Logic Journal

May 18, 2004

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