The Next Implementation Fabric: Issues and Considerations
by Andrew B. Kahng, Technical Program Co-Chair for Design Tools, 41st Design Automation Conference, Professor of CSE and ECE at the University of California, San Diego

The semiconductor industry is caught on two horns of the economics dilemma:

-- Technology scaling – sub-wavelength lithography, masks, and variability; and
-- Design productivity – turnaround time, and reusability of design effort.

Proliferation of semiconductors and their applications benefits from fast, cheap, and under-control ASIC-style implementation. Thus, the industry needs one or more implementation fabrics that support medium volume, lower cost, power and nonrecurring engineering (NRE) costs. To this end, several semiconductor technologies offer different visions of the next implementation fabric, as well as the application domains or cost-performance tradeoff points that such a fabric must support.

On one end of the flexibility spectrum, FPGA vendors offer programmable ICs with highly regular switching and logic fabrics; these offer designers near-zero NRE costs, low design costs and fast turnaround times. The tradeoff is that FPGA fabrics incur higher unit costs, lower integration densities and operating frequencies, and increased power dissipation.

At the other end of the spectrum, high-volume, low cost semiconductor designs have been well served by standard-cell based ASIC implementation methodology. The standard-cell fabric provides the lowest unit costs, fastest performance, and lowest power for the chip implementation. At 90 nanometers, however, the manufacturing NRE costs (mask set and probe card) of an ASIC design can reach $2 million. Nanometer-scale effects such as IR drop, electromigration and crosstalk must be analyzed and managed by the designer, which complicates performance closure and increases design cost. These challenges have contributed to a decrease in ASIC design starts from about 10,000 in 1998 to about 2,400 in 2003.

Positioned between ASIC and FPGA designs is the recently emerging “Structured ASIC” implementation category. A structured ASIC typically includes a pre-built base array constructed in an FPGA or MPGA (mask-programmed gate array) regular fabric; a given design is custom-manufactured with minimal final processing steps. Because the gate layers have the highest feature counts and most critical feature dimensions, it is more cost-effective if customization occurs only in the metal (wiring, via) layers. Thus, the interconnect layers in a structured ASIC may be either custom manufactured or programmable.

With their range of wire and via programmability options, structured ASIC fabrics today provide an innovative arena for semiconductor companies to offer chip designers alternative cost-performance tradeoff points. The structured ASIC concept combines smoothly with platform-based design when the base array is integrated with pre-qualified, domain-specific IP such as processor cores, memory, memory interfaces, serial I/O and bus interfaces, etc. Again, customization can be achieved with only a few, relatively inexpensive, metal- or via-layer masks.

The following figure compares these three categories of implementation fabric with respect to cost, power dissipation, performance and design turnaround time.

While EDA tools needed to design FPGA and ASIC chips are supplied by many EDA companies and foundries, the design of structured ASIC chips relies on software that is provided by only a handful of EDA vendors, or is foundry-supplied. If the history of previous implementation fabrics is any guide, we should expect to see the major EDA companies add new tools, and for new EDA companies to fill various gaps, so as to ease the design of structured ASICs.

Obviously, discussion and development will continue around the critical issue of whether a new design fabric is needed – and if so, which fabric. One of the best ways to learn more about this critical issue is to attend technical conferences, in particular, the Design Automation Conference, where more than 15,000 CAD developers, researchers, managers and engineers will gather from leading semiconductor companies, electronics companies, universities and the EDA industry. Anyone interested in what is happening with implementation fabrics – from both the design and EDA perspectives – should attend the 41 st annual Design Automation Conference being held in San Diego , June 7-11, 2004 .

Andrew B. Kahng, Technical Program Co-Chair for Design Tools, 41st Design Automation Conference
Professor of CSE and ECE at the University of California, San Diego.

May 18, 2004

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