DSP Heats Up
Synplicity Enters DSP Synthesis

This week, Synplicity announced they are joining the ranks of AccelChip, Altera, Xilinx and others in offering tools that help bridge the DSP-on-FPGA design gap. The brass ring is out there. It is easy to see that FPGAs with large arrays of embedded arithmetic elements have the potential for dominant DSP performance. Realizing that potential, however, is a matter of spanning one of the biggest “tool gaps” in electronic design automation today. While the promised performance benefits are staggering, (10-100X faster throughput than a typical DSP processor), the development effort penalty is equally enormous.

In reality, if you want to take your DSP algorithm to an FPGA instead of a DSP processor, you can expect at least 10X the development effort and similar jumps in design complexity and required expertise. The move from a primarily software implementation methodology to hardware design introduces the need for hardware architecture expertise and VHDL or Verilog coding skills. It also involves the use of synthesis, HDL simulation, place-and-route and timing analysis tools.

Most processor-based DSP development requires basic software skills for algorithm development in a tool such as MATLAB. The increased complexity of FPGA-based implementation usually means adding a specialized hardware designer to the team. This added design cost and complexity deters most teams from exploiting the performance, power, cost, and board space advantages available with FPGA-based DSP implementation.

Synplicity’s new tool, “Synplify DSP,” promises vendor-independence and a higher quality of results than vendor-based tools. It takes a different tack than AccelChip’s DSP synthesis product by using MathWorks’ Simulink as the “golden source” rather than native MATLAB M language. The goal of all these tools is to bridge the productivity and expertise barriers for DSP designers attempting hardware implementation.

Synplify DSP starts with algorithm development and refinement in Simulink using Synplicity’s DSP-specific fixed-point blockset. The Synplicity blockset includes functional blocks commonly used in DSP design such as filtering (FIR, IIR), transforms, math functions, CORDIC, signal operations, memories and control logic. During this process, fixed-point bit-widths are automatically chosen to preserve resolution, or bit-widths can be manually adjusted to achieve the desired tradeoff between hardware efficiency and signal-to-noise performance.

Synplify DSP then does what its name implies. It simplifies the DSP design process by automatically generating optimized RTL along with testbenches to be used in the hardware phase of the design. The auto-generated design is pre-configured to be compatible with Synplicity’s famously easy-to-use RTL synthesis tools, so the design process should not be too intimidating, even for designers with little or no hardware design experience. During the optimization process, the system also allows a multi-threaded implementation to be generated from a single channel specification. This provides a powerful latency, throughput, area tradeoff that can have a dramatic effect on the resulting design.

In all tools that generate architecture from behavior, the final proof is in the quality of results of the generated design. While RTL synthesis tools may differ by a few percent in their capabilities, tools generating RTL from algorithms are a completely different story. It is not uncommon to see an order of magnitude difference in quality of results between tools. In fact, within a single tool the designer often has enough control to affect a 5-10X tradeoff between, say, speed and area by varying the degree of parallelism versus resource sharing.

Synplify DSP allows you to perform what-if analysis on your design to determine the amount of pipelining required to reach the optimal tradeoff in throughput, latency, and hardware utilization. This optimization would be very difficult to perform in a manual hardware design flow, as each alternative requires an almost complete re-design of the RTL code. Since Synplify DSP allows this optimization to be done before RTL is generated, iteration and experimentation are quick and easy.

While FPGA vendors also offer tools that go from Simulink to FPGA, those tools typically require the use of vendor-specific IP blocks that lock you in to that vendor’s FPGA technology. Synplicity’s vendor-independent approach allows you to create your design in a vendor-independent way and retarget the design to different technologies or vendors, depending on your needs.

Synplicity’s tool is new and doesn’t yet have an established track record, but given the company’s reputation in developing leading-edge synthesis technology, chances are good that Synplify DSP will be a strong contender. Synplicity’s entry into this space also further validates that DSP-on-FPGA will be one of the hottest markets for both FPGA and tool vendors in the coming years.

Kevin Morris, FPGA and Programmable Logic Journal

May 11, 2004

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