A Matter of Integrity
SI Issues Hit FPGAs on Board

Remember engineering school? It was a time when life was simple, learning was fun, and a pencil line on a schematic meant that a logic input was “connected” to a corresponding output. Remember when you could design the pinout for your FPGA pretty much however you wanted, then throw it over the wall to some unknown engineer in the board team who, with equal disregard for the perilous potential of physics, would unceremoniously jam it onto a PCB with the idea that any old piece of metal coming into contact with the pins was probably good enough?

Well, if you’re out of engineering school now and off in the world of VHDL and Verilog designing digital delights for the new millennium, you probably were the type that didn’t prefer classes with words like “noise margins”, “impedance-matching”, and “transmission line”. If you had friends who did pay attention in those classes, however, now might be a good time to give them a call. You see, when your FPGA’s I/O pins started switching faster than about 40MHz, you earned an unexpected bonus. Any trace longer than one or two feet now includes a free antenna and transmission line. Now, in addition to connecting your inputs to your outputs, your PCB traces will do all sorts of new tricks you never imagined. Welcome to the world of ground bounce, ringing, and cross talk.

If you find some of these tricks to be less than amusing, you might need to roll up your sleeves, erase that pencil line, and replace it with a daunting network of inductors, resistors, capacitors, antennae, and transformers. These components have secretly been lurking there all these years just waiting for the chance to jump up and show you their stuff.

If you’re running at frequencies of 300MHz or more (which many of today’s I/O standards are) most all of your traces are behaving as transmission lines and antennas. Fortunately, we in the FPGA world are not the first to encounter this problem. Generations of brave high-frequency designers have come before us, and we can learn from their wisdom. The FPGA vendors want your design to work too, so they’ve done a lot of the worrying for you. Differential signal pairs such as those used in most serial I/O standards go a long way toward improving signal integrity. They solve a number of issues right out of the chute (although they bring in a few new challenges of their own). Let’s take a look at a few of the signal integrity (SI) related effects and walk through recommended design practices for getting around them.

First, if a receiver has a high impedance, and a driver has a low impedance, the resulting mismatch will cause reflections along the line. This causes the aforementioned “antenna” feature of the trace to radiate RF energy into space. If you’re not trying to build a transmitter, you’ll need to try to match the impedance as nearly as possible in order to reduce reflection. Unless you’re an analog savant, you’ll want to use a signal integrity package to model the drivers and receivers (see Donald Telian’s article on multi-gigahertz modeling techniques). This will allow you to determine where and how to add termination resistors (some devices provide on-chip support for this) to attenuate reflections and reduce radiation. Simulation tools such as Cadence’s Allegro PCB SI or Mentor’s Hyperlynx are popular solutions for SI simulation.

Second, if a wide bus of signals all decides to switch at the same time (at your direction, of course) the resulting load on the ground pin can cause “ground bounce.” This unexpected bump in the ground line can be seen as signal in adjoining lines, and it may insert some ones and zeros where you don’t want them. To design around this, make sure you have adequate power and ground connections, then properly add bypass capacitors and manage the simultaneous switching of parallel busses. Small vias through thick circuit boards can also exacerbate the problem. FPGA vendors have detailed application notes explaining standards for power and ground planes, supply design, and de-coupling and termination. It pays to understand and follow them. If you’re using high-speed serial lines instead of wide parallel busses this problem is also mitigated, but we promised we’d tell you about that part later.

Third, lines that run parallel to each other tend to couple. The resulting cross talk can be difficult to manage, and the only real solution is to keep traces physically separated, although an additional trace between the two can act as a chaperone and keep the cross coupling to a minimum. Here again, there are special rules for differential pairs that are, by design, always out of phase to minimize these effects.

To assist with all these problems, use the slowest slew rate that will work with your design, and the lowest drive strength. Since most SI problems are the result of errant energy, minimizing the power not only makes your design run cooler, it also reduces SI-related issues. Also, if you’re still using two-layer circuit boards and attempting today’s higher frequencies, your days of success are numbered. High frequency board design demands a modern power and ground plane, and board design techniques that may have worked in the past simply will not support today’s higher speeds.

Now, what about the predicted panacea of high-speed serial I/O? Well, first the good news. Two lines with differential signals and an embedded clock are much easier to manage on your circuit board than a 16-, 32-, or 64-bit synchronous bus. They consume far less real estate, demand fewer precious I/O pins, don’t require clock/bus synchronization, and have the nifty phase properties that increase noise immunity. If we were just trying to operate them at the same old megahertz speeds, it would be a walk in the park. We’re not content with that, however. Our need for speed has driven high speed serial into the gigahertz range, and they must be handled ever-so-carefully to make sure the data reaches its destination in order.

Most modern PCB routers can take differential pairs into account and keep them the required distance apart while maintaining matching trace lengths. On the FPGA side, I/O drivers have programmable pre-emphasis, which compensates for differences in packaging, board trace, and receiver impedance by sending a larger magnitude signal at transition boundaries. Synchronization with a separate clock line is not required with these standards, as the clock is re-created at the receiver end using clock/data recovery where the clock is inferred from the frequency of transitions of the data.

Know what an eye-diagram is? (No, it’s not the chart at the doctor’s office with the big E at the top.) Eye diagrams are created by synchronizing a number of signal transitions with a reference clock, tracing them on a scope, and examining the thickness of the trace overlap (to understand voltage noise and jitter). The size and shape of the “hole” between the traces determine the timing and voltage margins available to a receiver interpreting the signal. Eye diagrams are one of the most commonly used tools for visualizing the operating margins of high-speed signals, so it pays to understand them.

Does all this make you wish for the simple days of Karnaugh maps and Boolean bliss? Well, school’s out and this is the real world. Think of it as an opportunity to meet new people (like the nice board designers down the hall), or to get in touch with those long-lost buddies that paid attention in analog class.

Kevin Morris, FPGA and Programmable Logic Journal

April 27, 2004

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