Fast and Accurate Multi-GigaHertz Modeling Techniques
Donald Telian, Cadence Design Systems, Inc.

As differential signal frequencies rise, Multi-GigaHertz (MGH) system simulation becomes imperative. This is particularly true as systems and packages become harder to probe, and signals become perceptible only to equalization embedded within silicon. Yet silicon-package-board modeling is at a crossroads; IBIS can’t handle pre-emphasis and transistor models are too slow to simulate enough bits. Has this issue affected your design team?

New techniques are now available for your MGH simulations that are probably simpler than you think. In this article we’ll look at why these solutions are important and explain some basic understandings you’ll need to apply them. Read on, and you’ll discover that your next step forward is only a couple mouse clicks away.

Wide Eyes and More Bits

Serial MGH transceivers are designed to adapt and function amidst a wide variety of system interconnects, or “channels”. Often these channels are far from ideal, exhibiting various loss and impedance discontinuities and mismatches. Short simulations can often reveal these problems, help find solutions, and demonstrate that the differential signal voltages are switching as expected.

However, non-ideal channels can also exhibit behaviors that are harder to understand and quantify. Certain bit patterns can combine with unterminated energy in the system to produce unexpected results. Although encoding schemes like 8b/10b serve to reduce the number of potential bit combinations, it is difficult to fully verify a channel without testing long bit streams. “Long” in this case is proportional to the bit variations expected when overlaid against the channel’s settling time or “memory”.

The need to verify a channel against a long bit stream is illustrated in Figure 1. This figure shows the shrinking eye height of an MGH serial link when simulating an increasing amount of bits. Notice how the eye height after 20,000 bits is reduced to 60% of that measured after 300 bits. Indeed, the eye height of non-ideal channels may decrease rapidly through the first 100,000 bits before the measured performance of the channel converges. This magnitude of variation can cause failures in a system design you expect to work correctly.

Figure 1 – Eye height shrinks with more simulated bits

The Need for Faster Models

To comprehend the behavior of your channel against longer bit patterns a model of the silicon that simulates faster must be found. While transistor-level models are well-trusted for their accuracy, they are also known to require a long time to simulate even a couple hundred bits. A typical transistor-level model simulation completing 100 bits per hour needs well over a year to simulate a million bits. This is obviously not acceptable.

To address this challenge, Cadence offers downloadable “MacroModel” templates you can use to quickly form models of your MGH devices. Because they are optimized and behavioral, these models typically simulate hundreds of times faster than transistor-level models. Using this type of model puts long bit-stream simulation – and hence better channel validation - within your grasp.

At the end of this article I’ll explain where to get the model templates, but first let’s look at a couple critical things you’ll need to understand to use them effectively.

Understanding Pre-emphasis

The majority of MGH transceivers in the 1 to 5 GHz range utilize something called 2-tap “pre-emphasis”. You may be familiar with this term yet not clear about how it is implemented, and hence unclear about how to model it. Yet this is the distinguishing feature that causes these transmitters to not work well within the behavioral IBIS model structure. To pursue this discussion, I’ll assume you understand the basic elements in an IBIS model yet need to know what is different about transmitters with pre-emphasis.

Figure 2 shows the basic elements in a differential transmitter. Everything to the left of the dashed line can be handled with IBIS and should look familiar. The signal is both driven high and terminated through a resistor, and driven low using the blue transistor of size N connected to ground. The pre-emphasis elements to the right of the dashed line add an inverter, a unit interval delay “UI dly”, and another transistor. This extra red transistor is a scaled-down version of the blue one, of size N/x, and is connected in parallel.

Figure 2 – Basic structure of a pre-emphasis transmitter and model

Pre-emphasis uses these extra elements to flatten the frequency response of the channel. The extra transistor stage in red accomplishes this by boosting the high-frequency switching bits, while attenuating the lower-frequency repetitive bits. You can see this by studying the color matched waveforms in Figure 3. The blue waveform is the normal IBIS-like switching of the blue transistor. The red waveform is driven by the red transistor and is an inverted, scaled-down, one-UI-delayed version of the blue waveform. Be sure to study the blue and red waveforms carefully until the previous sentence makes sense.

Since the blue and red transistors are tied together on the output pin, they combine to produce the black waveform which looks like a signal with pre-emphasis. The resulting waveform correctly switches the larger amplitude on high-frequency transition bits, yet drops amplitude on the lower-frequency non-transition bits.

Figure 3 – MGH signals from each stage and the stages combined

How to Build Your MGH MacroModel

From this discussion you can see that this switching behavior can easily be modeled in the MacroModel templates when you supply two additional pieces of information: the unit interval, and the scale factor X. If you do not know X from the transistor design, it can also be derived from the pre-emphasis’ decrease in amplitude which is often expressed in dB as 20*log(V_final/V_initial). And the unit interval is simply the bit period; for example, 400 pS at 2.5 Gbps.

To form your MacroModel using the template, follow these steps:

1. build the IBIS model of the circuit to the left of the dashed line in Figure 2 (turn pre-emphasis “off” and use your normal modeling process)
   
2. supply parameters for both the dB decrease and the bit period
   
3. if you are matching an existing transistor model, adjust the additional correlation parameters in the template until your waveforms match as desired

Once this is done, you will have a fast and accurate model of your MGH transmitter you can use to simulate long bit streams and design a more robust MGH serial link.

And “robust” design and operation is quite important in serial links. Engineers are finding out that, unlike parallel busses, re-transmission schemes cause serial hardware to appear to work correctly even though many bits are failing. As such, the actual throughput can be far below what you expect if you do not adequately simulate and verify your design.

How to Get Your MacroModel Templates

You can get a well-documented set of MGH template models by submitting your request on the web at: http://register.cadence.com/register.nsf/macroModeling?OpenForm.
Further help with the models is available in whitepapers, webinars, and other info accessible at http://www.pcbhighspeed.com/TechnicalPapers.asp, http://www.cadence.com/webinars/webinars.aspx?xml=pcbmacromodeling, and http://www.AllegroSI.com/Optimize/O_Models.asp#macromodels .
There are also helpful examples of this type of model and advice on their optimal use in the Design Kits – particularly the new PCI Express Design-in Kit - found at http://www.AllegroSI.com/Optimize/DesignKits.asp.
The models can be used in both the Cadence Allegro PCB SI and Allegro Package SI analysis environments.

Conclusion

It’s important to verify your serial link channel design using simulation. In non-ideal channels, simulations need to comprehend tens and even hundreds of thousands of bit variations. You can build faster models to perform this kind of simulation by downloading MacroModel templates and modifying them as required, leveraging the various resources and examples provided above.

Donald Telian, Cadence Design Systems, Inc.

April 27, 2004

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