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May 13, 2008 - This week, Bryon Moyer takes us back across the analog/digital divide with a look at high-speed serial and JESD204.  With billions of bits blasting through just two wires every second, the analog world comes crashing into our comfy little digital domain like a truck with no brakes.  Bryon's latest feature has the details.

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Techfocus Media, Inc.

High-Speed Serial Comes to the Analog/Digital Divide
Lattice and Linear Technology Collaborate on JESD204 (Bryon Moyer)

Everyone knows that if you want to do things slowly, you do them one at a time. If you want to get more done, you get more people to help do things in parallel. Right? I mean, in the world of electronics, think “serial,” and what might come to mind is the slow, stately procession of bits plodding from your desktop to some not-very-needy peripheral. You want speed? Check out the parallel port, where multiple lines are willing and able to deliver the kind of data demanded by your more high-maintenance attention-craving peripherals.

Historically, this was also the case when hooking chips together on a board; any kind of real data transfer went on a bus, which by definition, consisted of parallel lines. And they got faster… and faster… until a couple of problems started to crop up. From an electrical standpoint, somewhere along the way you end up switching so fast that you actually can have multiple pulses on a wire at the same time, strung along, marching towards the end. And you’ve got a bunch of these wires, and they damn well better be EXACTLY the same length, or else you might mistakenly interpret line 5’s 791st bit as the 792nd bit. And with jitter, that could happen intermittently.

Oh, and then there’s the problem of how to clock the dang thing. Especially if you’re going across a backplane from one board to the other, and where there’s no master clock for both boards. If things are slow, well, slight differences in clock phase and frequency, if they matter at all, can be accommodated by FIFOs, or heck, even just double-buffering to harden against metastability. For those of you liking million-dollar words, such a system is called plesiochronous, meaning that it’s more or less synchronous, but there may be clock differences within some specified limit. [more]

Golden Hammer
Pursuit of the Programmable Panacea (Kevin Morris)

The countdown counter/timer circuit was pretty trivial to code up in VHDL.  My dev board had an old FPGA on it, but it didn’t matter.  The original version of my little design probably used less than 10% of the chip anyway.  I’d enhanced it several times, of course.  The original one loaded a big number into the register and then counted down.  When the countdown reached zero, an audio-frequency square wave was generated at an output pin.  A little amplifier circuit took the digital signal and ran it straight to a small speaker producing the desired effect – a buzzy tone that was clearly audible. 

Version two had a bit more capability.  I keyed a button on the development board to first stop the buzzing tone, then load a new (much smaller) value into the countdown register and start the countdown again.  Now, there were two controls – the master reset that configured the FPGA and started the big countdown and the new control that stopped the buzz and re-started the delay timer with a smaller value.  I also figured out that I could run the counter at audio frequencies and simply use the clock signal as the tone generator when the count reached zero.  Slowing down the clock also allowed the use of a smaller countdown register to reach my target delay – about eight hours. [more]

Playing Pin Twister
Taray Attempts to Untangle FPGA Pin Assignment (Bryon Moyer)

Once upon a time, PLD pinouts were an easy thing. Oh, yeah, sorry… for you neophytes, that’s “Programmable Logic Device,” a term once ubiquitous, and still relevant, except that FPGAs are the overwhelmingly dominant survivor. So much so that some people think of PLDs as just the small non-volatile glue-mop-up devices, to paint an ugly mixed-metaphorical picture, even though an FPGA is no less programmable a device. Back in the day, when you were writing your Boolean equations in PALASM for your PAL16L8 (OK, I know I’ve lost a generation of you now), you simply listed the mnemonics you were going to use for the pin names on all 20 pins in order. Yeah, only 20… remember SKINNYDIP packages? (You youngsters can stop blushing now; we were a wild generation, work it out with your therapists.) [more]

How To Implement SystemVerilog for FPGA Design
by Ehab Mohsen, Mentor Graphics Corporation

Introduction
Since its ratification in 2005, the SystemVerilog IEEE-1800 standard has experienced broad adoption in the verification and assertion space but has lagged for design constructs. Engineers may be wary of revamping current design methodologies, or they assume that SystemVerilog for design is not relevant to their projects, or they fear that field-programmable gate array (FPGA) synthesis tools do not fully support the new standard. All three of these concerns are either exaggerated or based on misconceptions. SystemVerilog is fully supported by leading synthesis tools, and the new design constructs are in fact relevant to most register-transfer level (RTL) coding styles and easy to learn and integrate into current methodologies. [more]

Merging with Agility
Alliance Unlocks FPGA Potential
(Kevin Morris)

We’ve talked many times about the potential of FPGAs in providing incredible amounts of the Good kind of power (computing) while consuming comparatively tiny amounts of the Bad kind of power (“juice”).  When you want a lot of numbers manipulated very quickly with the least possible amount of juice, a highly parallelized datapath implemented in the programmable fabric of an FPGA is hard to beat.  That’s why we have groups like the die-hard fringe of supercomputing – the “reconfigurable computing community” struggling for decades to build a tool infrastructure that can more easily get more of those big ’ol algorithms squished down into FPGAs. [more]

Synplicity Gets Spirit
ReadyIP Announcement has Bigger Implications (Kevin Morris)

While the word “ecosystem” is happily bantered about by major FPGA vendors, history would indicate that FPGA companies are less than perfect participants in the care and feeding of “ecosystems” to support their products.  The turmoil associated with the love/hate, competitor/partner, customer/supplier relationships between FPGA companies and others providing various products and services to the FPGA community are well documented.  [more]

One to Many
FPGA Design Diversifies (Kevin Morris)

About a decade ago, FPGA design followed in the footsteps of ASIC and went language-based.  For a very long time, the only question we asked ourselves was “VHDL or Verilog?”  It was reminiscent of the “Paper or Plastic?” scenario in the grocery checkout line.  Gradually, however, people sneaked into the FPGA-designing fold that weren’t FPGA designers.  Who are these folks anyway?  We’ve got DSP engineers, embedded systems designers, board designers, supercomputing folks… the list goes on and on. 

Apparently all those new engineers didn’t get the memo about conforming to our established design methodologies, or else they just didn’t feel like becoming experts in VHDL and Verilog.  Compounding the problem was the fact that FPGA and EDA companies – money-grubbing monsters that they are -- decided to actually cater to these interlopers by giving them gold-plated, easy-as-pie design entry mechanisms that allowed them to almost completely forego the time-honored traditions of entities and architectures.  [more]

Tools and Transceivers
Dual Xilinx Announcements (Kevin Morris)

In the old days, we had only two kinds of FPGA – small and smaller, also known as slow and slower, or hot and hotter...  The technology was useful for a few high-value applications, but it was limited on all three fronts – density (cost), speed, and power -- from attacking a much broader market.  As we waltzed along the to the three-count meter of Moore’s Law, all three critical parameters improved.  Density went up, frequency got faster, power cooled down, and people got happier.

After a few rounds, however, FPGAs had pretty well saturated the bigger, faster, cooler crowd.  In order to reach a broader audience now, we needed to teach our favorite semiconductors some new tricks.  For the DSP people, we designed hardened high-speed multipliers.  For connectivity hogs, we grafted on multi-gigabit serial transceivers.  For embedded designers, we dropped in a processor core or two – and all of those people needed big blocks of memory to make effective use of the new features. [more]

Methods for Reducing Marketing Jitter Through Filtering of Marketing Noise in Conference Presentations (Bryon Moyer)

Related Applications
None

Field of the Invention
Way out in left field.

Background of the Invention
For purposes of gathering together for reasons including but not limited to sharing information, making commercial announcements, receiving training, professional networking, escaping a nagging spouse or children, and racking up frequent flier miles, it is common for engineering professionals to attend conferences or conventions. [more]